Datasheet

156
11011B–ATARM–21-Feb-12
SAM3N
10.20.5 Interrupt Clear-pending Registers
The ICPR0 register removes the pending state from interrupts, and show which interrupts are
pending. See:
• the register summary in Table 10-27 on page 151 for the register attributes
• Table 10-28 on page 152 for which interrupts are controlled by each register.
The bit assignments are:
• CLRPEND
Interrupt clear-pending bits.
Write:
0 = no effect.
1 = removes pending state an interrupt.
Read:
0 = interrupt is not pending.
1 = interrupt is pending.
Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
31 30 29 28 27 26 25 24
CLRPEND
23 22 21 20 19 18 17 16
CLRPEND
15 14 13 12 11 10 9 8
CLRPEND
76543210
CLRPEND