Datasheet

155
11011B–ATARM–21-Feb-12
SAM3N
10.20.4 Interrupt Set-pending Registers
The ISPR0 register forces interrupts into the pending state, and shows which interrupts are
pending. See:
• the register summary in Table 10-27 on page 151 for the register attributes
• Table 10-28 on page 152 for which interrupts are controlled by each register.
The bit assignments are:
• SETPEND
Interrupt set-pending bits.
Write:
0 = no effect.
1 = changes interrupt state to pending.
Read:
0 = interrupt is not pending.
1 = interrupt is pending.
Writing 1 to the ISPR bit corresponding to:
• an interrupt that is pending has no effect
• a disabled interrupt sets the state of that interrupt to pending
31 30 29 28 27 26 25 24
SETPEND
23 22 21 20 19 18 17 16
SETPEND
15 14 13 12 11 10 9 8
SETPEND
76543210
SETPEND