Datasheet

154
11011B–ATARM–21-Feb-12
SAM3N
10.20.3 Interrupt Clear-enable Registers
The ICER0 register disables interrupts, and shows which interrupts are enabled. See:
• the register summary in Table 10-27 on page 151 for the register attributes
• Table 10-28 on page 152 for which interrupts are controlled by each register
The bit assignments are:
•CLRENA
Interrupt clear-enable bits.
Write:
0 = no effect
1 = disable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
31 30 29 28 27 26 25 24
CLRENA
23 22 21 20 19 18 17 16
CLRENA
15 14 13 12 11 10 9 8
CLRENA
76543210
CLRENA