Datasheet

152

11011B–ATARM–21-Feb-12

SAM3N

• the 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the

array IP[0] to IP[32] corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds

the interrupt priority for interrupt n.

The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Regis-

ters. For more information see the description of the NVIC_SetPriority function in “NVIC

programming hints” on page 163. Table 10-28 shows how the interrupts, or IRQ numbers, map

onto the interrupt registers and corresponding CMSIS variables that have one bit per interrupt.

Table 10-28. Mapping of interrupts to the interrupt variables

Interrupts

CMSIS array elements

(1)

1. Each array element corresponds to a single NVIC register, for example the element

ICER[0]

corresponds to the ICER0 register.

Set-enable Clear-enable Set-pending Clear-pending Active Bit