Datasheet

151
11011B–ATARM–21-Feb-12
SAM3N
10.20 Nested Vectored Interrupt Controller
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:
• 1 to 33 interrupts.
• A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.
• Level and pulse detection of interrupt signals.
• Dynamic reprioritization of interrupts.
• Grouping of priority values into group priority and subpriority fields.
• Interrupt tail-chaining.
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling. The
hardware implementation of the NVIC registers is:
10.20.1 The CMSIS mapping of the Cortex-M3 NVIC registers
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the
CMSIS:
• the Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to
arrays of 32-bit integers, so that:
– the array
ISER[0] corresponds to the registers ISER0
– the array
ICER[0] corresponds to the registers ICER0
– the array
ISPR[0] corresponds to the registers ISPR0
– the array
ICPR[0] corresponds to the registers ICPR0
– the array
IABR[0] corresponds to the registers IABR0
Table 10-27. NVIC register summary
Address Name Type
Required
privilege
Reset
value Description
0xE000E100
ISER0 RW Privileged 0x00000000 “Interrupt Set-enable Registers” on page 153
0xE000E180 ICER0
RW Privileged 0x00000000 “Interrupt Clear-enable Registers” on page 154
0xE000E200
ISPR0 RW Privileged 0x00000000 “Interrupt Set-pending Registers” on page 155
0xE000E280 ICPR0
RW Privileged 0x00000000 “Interrupt Clear-pending Registers” on page 156
0xE000E300 IABR0
RO Privileged 0x00000000 “Interrupt Active Bit Registers” on page 157
0xE000E400-
0xE000E41C
IPR0-
IPR8
RW Privileged 0x00000000 “Interrupt Priority Registers” on page 158
0xE000EF00 STIR WO
Configurable
(1)
0x00000000
“Software Trigger Interrupt Register” on page
161
1. See the register description for more information.