Datasheet

150
11011B–ATARM–21-Feb-12
SAM3N
10.19 About the Cortex-M3 peripherals
The address map of the Private peripheral bus (PPB) is:
In register descriptions:
• the register type is described as follows:
RW Read and write.
RO Read-only.
WO Write-only.
• the required privilege gives the privilege level required to access the register, as follows:
Privileged Only privileged software can access the register.
Unprivileged Both unprivileged and privileged software can access the register.
Table 10-26. Core peripheral register regions
Address Core peripheral Description
0xE000E008 -
0xE000E00F
System control block Table 10-30 on page 164
0xE000E010 -
0xE000E01F
System timer Table 10-33 on page 191
0xE000E100 -
0xE000E4EF
Nested Vectored Interrupt
Controller
Table 10-27 on page 151
0xE000ED00 -
0xE000ED3F
System control block Table 10-30 on page 164
0xE000ED90 -
0xE000ED93
MPU Type Register
Reads as zero, indicating no MPU is
implemented
(1)
1. Software can read the MPU Type Register at 0xE000ED90 to test for the presence of a memory
protection unit (MPU).
0xE000EF00 -
0xE000EF03
Nested Vectored Interrupt
Controller
Table 10-27 on page 151