Datasheet

137
11011B–ATARM–21-Feb-12
SAM3N
10.18 Miscellaneous instructions
Table 10-25 shows the remaining Cortex-M3 instructions:
Table 10-25. Miscellaneous instructions
Mnemonic Brief description See
BKPT Breakpoint “BKPT” on page 138
CPSID
Change Processor State, Disable
Interrupts
“CPS” on page 139
CPSIE
Change Processor State, Enable
Interrupts
“CPS” on page 139
DMB Data Memory Barrier “DMB” on page 140
DSB Data Synchronization Barrier “DSB” on page 141
ISB Instruction Synchronization Barrier “ISB” on page 142
MRS Move from special register to register “MRS” on page 143
MSR Move from register to special register “MSR” on page 144
NOP No Operation “NOP” on page 145
SEV Send Event “SEV” on page 146
SVC Supervisor Call “SVC” on page 147
WFE Wait For Event “WFE” on page 148
WFI Wait For Interrupt “WFI” on page 149