Datasheet

118
11011B–ATARM–21-Feb-12
SAM3N
10.13.9 TST and TEQ
Test bits and Test Equivalence.
10.13.9.1 Syntax
TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
where:
cond is an optional condition code, see “Conditional execution” on page 84.
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See “Flexible second operand” on page 80 for
details of the options.
10.13.9.2 Operation
These instructions test the value in a register against Operand2. They update the condition flags
based on the result, but do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of
Operand2. This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has
that bit set to 1 and all other bits cleared to 0.
The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value
of Operand2. This is the same as the EORS instruction, except that it discards the result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical
Exclusive OR of the sign bits of the two operands.
10.13.9.3 Restrictions
Do not use SP and do not use PC
.
10.13.9.4 Condition flags
These instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of Operand2, see “Flexible second operand” on
page 80
• do not affect the V flag.
10.13.9.5 Examples
TST R0, #0x3F8 ; Perform bitwise AND of R0 value to 0x3F8,
; APSR is updated but result is discarded
TEQEQ R10, R9 ; Conditionally test if value in R10 is equal to
; value in R9, APSR is updated but result is discarded