Datasheet

106
11011B–ATARM–21-Feb-12
SAM3N
• Rd can be SP only in ADD and SUB, and only with the additional restrictions:
– Rn must also be SP
– any shift in Operand2 must be limited to a maximum of 3 bits using LSL
• Rn can be SP only in ADD and SUB
• Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
– you must not specify the S suffix
– Rm must not be PC and must not be SP
– if the instruction is conditional, it must be the last instruction in the IT block
• with the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and
SUB, and only with the additional restrictions:
– you must not specify the S suffix
– the second operand must be a constant in the range 0 to 4095.
–
– When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded
to b00 before performing the calculation, making the base address for the calculation
word-aligned.
– If you want to generate the address of an instruction, you have to adjust the constant
based on the value of the PC. ARM recommends that you use the ADR instruction
instead of ADD or SUB with Rn equal to the PC, because your assembler
automatically calculates the correct constant for the ADR instruction.
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
10.13.1.4 Condition flags
If S is specified, these instructions update the N, Z, C and V flags according to the result.
10.13.1.5 Examples
ADD R2, R1, R3
SUBS R8, R6, #240 ; Sets the flags on the result
RSB R4, R4, #1280 ; Subtracts contents of R4 from 1280
ADCHI R11, R0, R3 ; Only executed if C flag set and Z
; flag clear