Features • Core • • • • • • • – ARM® Cortex®-M3 revision 2.
1. SAM3N Description Atmel's SAM3N series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 48 MHz and features up to 256 Kbytes of Flash and up to 24 Kbytes of SRAM. The peripheral set includes 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, as well as 1 PWM timer, 6x general purpose 16-bit timers, an RTC, a 10-bit ADC and a 10-bit DAC.
SAM3N 1.1 Configuration Summary The SAM3N4/2/1/0/00 differ in memory size, package and features list. Table 1-1 summarizes the configurations of the 9 devices. Table 1-1.
2. SAM3N Block Diagram System Controller UT VD DO VD DI N JT AG SE L SAM3N 100-pin version Block Diagram TD TDI O TM /TR S A TC /SW CE K/ D SW SW IO O CL K Figure 2-1.
SAM3N System Controller UT VD DO VD DI N JT AG SE L SAM3N 64-pin version Block Diagram TD TDI O TM /TR S A TC /SW CE K/ D SW SW IO O CL K Figure 2-2.
System Controller UT VD DO VD DI N JT AG SE L SAM3N 48-pin version Block Diagram TD TDI O TM /TR S A TC /SW CE K/ D SW SW IO O CL K Figure 2-3.
SAM3N 3. Signal Description Table 3-1 gives details on the signal name classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripherals I/O Lines Power Supply Power 1.62V to 3.6V VDDIN Voltage Regulator, ADC and DAC Power Supply Power 1.8V to 3.6V(3) VDDOUT Voltage Regulator Output Power 1.8V Output VDDPLL Oscillator and PLL Power Supply Power 1.65 V to 1.
Table 3-1.
SAM3N Table 3-1.
4. Package and Pinout SAM3N4/2/1/0/00 series is pin-to-pin compatible with SAM3S products. Furthermore SAM3N4/2/1/0/00 devices have new functionalities referenced in italic inTable 4-1, Table 4-3 and Table 4-4. 4.1 4.1.1 SAM3N4/2/1/0/00C Package and Pinout 100-lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 75 51 76 50 100 26 1 4.1.2 25 100-ball TFBGA Package Outline The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards.
SAM3N 4.1.3 100-Lead LQFP Pinout Table 4-1.
4.1.4 100-ball TFBGA Pinout Table 4-2.
SAM3N 4.2 SAM3N4/2/1/0/00B Package and Pinout Figure 4-3. Orientation of the 64-pad QFN Package 64 49 1 48 16 33 32 17 Figure 4-4.
4.2.1 64-Lead LQFP and QFN Pinout 64-pin version SAM3N devices are pin-to-pin compatible with SAM3S products. Furthermore, SAM3N products have new functionalities shown in italic in Table 4-3. Table 4-3.
SAM3N 4.3 SAM3N4/2/1/0/00A Package and Pinout Figure 4-5. Orientation of the 48-pad QFN Package 48 37 1 36 12 25 13 24 TOP VIEW Figure 4-6.
4.3.1 48-Lead LQFP and QFN Pinout Table 4-4.
SAM3N 5. Power Considerations 5.1 Power Supplies The SAM3N product has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals. Voltage ranges from 1.62V to 1.95V. • VDDIO pins: Power the Peripherals I/O lines, Backup part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62V to 3.6V • VDDIN pin: Voltage Regulator, ADC and DAC Power Supply. Voltage ranges from 1.8V to 3.
Figure 5-1. Single Supply VDDIO I/Os. Main Supply (1.8V-3.6V) ADC, DAC VDDIN VDDOUT Voltage Regulator VDDCORE VDDPLL Figure 5-2. Core Externally Supplied Main Supply (1.62V-3.6V) VDDIO I/Os. Can be the same supply ADC, DAC Supply (3V-3.6V) ADC, DAC VDDIN VDDOUT VDDCORE Supply (1.62V-1.95V) Voltage Regulator VDDCORE VDDPLL Note: Restrictions With Main Supply < 3V, ADC and DAC are not usable. With Main Supply >= 3V, all peripherals are usable.
SAM3N Figure 5-3. Core Externally Supplied (backup battery) ADC, DAC Supply (3V-3.6V) Backup Battery VDDIO I/Os. + ADC, DAC VDDIN Main Supply IN OUT 3.3V LDO VDDOUT Voltage Regulator VDDCORE ON/OFF VDDPLL PIOx (Output) WAKEUPx External wakeup signal Note: The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode. 5.
• Supply Monitor alarm • RTC alarm • RTT alarm 5.5.2 Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of less than 10 µs. Current Consumption in Wait mode is typically 15 µA (total current consumption) if the internal voltage regulator is used or 8 µA if an external regulator is used. In this mode, the clocks of the core, peripherals and memories are stopped.
SAM3N 5.5.4 Low Power Mode Summary Table The modes detailed above are the main low power modes. Each part can be set to on or off separately and wake up sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low power modes. Table 5-1.
5.6 Wake-up Sources The wake-up events allow the device to exit backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled. Figure 5-4.
SAM3N 5.7 Fast Start-Up The SAM3N allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT). The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast startup signal to the Power Management Controller.
6. Input/Output Lines The SAM3N has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in IO mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs. 6.1 General Purpose I/O Lines GPIO Lines are managed by PIO Controllers.
SAM3N Table 6-1. System I/O Configuration Pin List. SYSTEM_IO bit number Default function after reset Other function 12 ERASE PB12 Low Level at startup(1) 7 TCK/SWCLK PB7 - 6 TMS/SWDIO PB6 - 5 TDO/TRACESWO PB5 - 4 TDI PB4 - - PA7 XIN32 - - PA8 XOUT32 - - PB9 XIN - - PB8 XOUT - Notes: Constraints for normal start Configuration In Matrix User Interface Registers (Refer to the System I/O Configuration Register in the Bus Matrix section of the product datasheet.
6.3 Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3N series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, see the “Fast Flash Programming Interface” section of the product datasheet. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet. 6.
SAM3N 7. Product Mapping 7.1 Product Mapping Figure 7-1.
7.2 7.2.1 Embedded Memories Internal SRAM The SAM3N4 product embeds a total of 24-Kbytes high-speed SRAM. The SAM3N2 product embeds a total of 16-Kbytes high-speed SRAM. The SAM3N1 product embeds a total of 8-Kbytes high-speed SRAM. The SAM3N0 product embeds a total of 8-Kbytes high-speed SRAM. The SAM3N00 product embeds a total of 4-Kbytes high-speed SRAM. The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000. The SRAM is in the bit band region.
SAM3N The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic. 7.2.3.4 Flash Speed The user needs to set the number of wait states depending on the frequency used.
7.2.3.7 Calibration Bits NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits. 7.2.3.8 Unique Identifier Each device integrates its own 128-bit unique identifier. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the unique identifier. 7.2.3.
SAM3N 8. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc... See the System Controller block diagram in Figure 8-1 on page 32.
Figure 8-1.
SAM3N 8.1 System Controller and Peripheral Mapping Please refer to Figure 7-1, "SAM3N4/2/1/0/00 Product Mapping" on page 27. All the peripherals are in the bit band region and are mapped in the bit band alias region. 8.2 Power-on-Reset, Brownout and Supply Monitor The SAM3N embeds three features to monitor, warn and/or reset the chip: • Power-on-Reset on VDDIO • Brownout Detector on VDDCORE • Supply Monitor on VDDIO 8.2.1 Power-on-Reset The Power-on-Reset monitors VDDIO.
9. Peripherals 9.1 Peripheral Identifiers Table 9-1 defines the Peripheral Identifiers of the SAM3N4/2/1/0/00. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 9-1.
SAM3N 9.2 APB/AHB Bridge The SAM3N4/2/1/0/00 product embeds one peripheral bridge: The peripherals of the bridge are clocked by MCK. 9.3 Peripheral Signal Multiplexing on I/O Lines The SAM3N product features 2 PIO controllers (48-pin and 64-pin version) or 3 PIO controllers (100-pin version), PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. The SAM3N 64-pin and 100-pin PIO Controller controls up to 32 lines (see Table 9-2, “Multiplexing on PIO Controller A (PIOA),” on page 36).
9.3.1 PIO Controller A Multiplexing Table 9-2.
SAM3N 9.3.2 Table 9-3.
9.3.
SAM3N 10. ARM Cortex® M3 Processor 10.1 About this section This section provides the information required for application and system-level software development. It does not provide information on debug components, features, or operation. This material is for microcontroller software and hardware engineers, including those who have no experience of ARM products. Note: The information in this section is reproduced from source material provided to Atmel by ARM Ltd.
• enhanced system debug with extensive breakpoint and trace capabilities • efficient processor core, system and memories • ultra-low power consumption with integrated sleep modes Figure 10-1.
SAM3N 10.3.1 System level interface The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide high speed, low latency memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data handling. 10.3.2 Integrated configurable debug The Cortex-M3 processor implements a complete hardware debug solution.
10.4 Programmers model This section describes the Cortex-M3 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 10.4.1 Processor mode and privilege levels for software execution The processor modes are: 10.4.1.1 Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. 10.4.1.2 Handler mode Used to handle exceptions.
SAM3N In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack, see “CONTROL register” on page 52. In Handler mode, the processor always uses the main stack. The options for processor operations are: Table 10-1. Processor mode Used to execute Privilege level for software execution Stack used Thread Applications Privileged or unprivileged (1) Main stack or process stack(1) Handler Exception handlers Always privileged Main stack 1. 10.4.
Table 10-2.
SAM3N 10.4.3.4 Program Counter The Program Counter (PC) is register R15. It contains the current program address. Bit[0] is always 0 because instruction fetches must be halfword aligned. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x00000004.
10.4.3.5 Program Status Register The Program Status Register (PSR) combines: • Application Program Status Register (APSR) • Interrupt Program Status Register (IPSR) • Execution Program Status Register (EPSR). These registers are mutually exclusive bitfields in the 32-bit PSR.
SAM3N The PSR bit assignments are: 31 30 29 28 27 N Z C V Q 23 22 21 20 26 25 ICI/IT 19 18 11 10 24 T 17 16 Reserved 15 14 13 12 ICI/IT 7 6 5 4 3 2 9 8 Reserved ISR_NUMBER 1 0 ISR_NUMBER Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions.
• C Carry or borrow flag: 0 = add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1 = add operation resulted in a carry bit or subtract operation did not result in a borrow bit. • V Overflow flag: 0 = operation did not result in an overflow 1 = operation resulted in an overflow.
SAM3N 10.4.3.8 Execution Program Status Register The EPSR contains the Thumb state bit, and the execution state bits for either the: • If-Then (IT) instruction • Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. See the register summary in Table 10-2 on page 44 for the EPSR attributes. The bit assignments are: • ICI Interruptible-continuable instruction bits, see “Interruptible-continuable instructions” on page 49.
10.4.3.12 Priority Mask Register The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary in Table 10-2 on page 44 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 0 Reserved PRIMASK • PRIMASK 0 = no effect 1 = prevents the activation of all exceptions with configurable priority. 10.4.3.
SAM3N 10.4.3.14 Base Priority Mask Register The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. See the register summary in Table 10-2 on page 44 for its attributes.
10.4.3.15 CONTROL register The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. See the register summary in Table 10-2 on page 44 for its attributes.
SAM3N 10.4.4 Exceptions and interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset. See “Exception entry” on page 69 and “Exception return” on page 70 for more information. The NVIC registers control interrupt handling.
• “Power management programming hints” on page 74 • “Intrinsic functions” on page 78 • “The CMSIS mapping of the Cortex-M3 NVIC registers” on page 151 • “NVIC programming hints” on page 163.
SAM3N 10.5 Memory model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. The memory map is: 0xFFFFFFFF Vendor-specific memory 511MB 0xE0100000 0xE00FFFFF Private peripheral 1.0MB bus 0xE0000000 0xDFFFFFFF External device 1.0GB 0xA0000000 0x9FFFFFFF External RAM 0x43FFFFFF 1.
10.5.1.1 Normal The processor can re-order transactions for efficiency, or perform speculative reads. 10.5.1.2 Device The processor preserves transaction order relative to other transactions to Device or Stronglyordered memory. 10.5.1.3 Strongly-ordered The processor preserves transaction order relative to all other transactions.
SAM3N < Means that accesses are observed in program order, that is, A1 is always observed before A2. 10.5.3 Behavior of memory accesses The behavior of accesses to each region in the memory map is: Table 10-4. Memory access behavior Address range Memory region Memory type XN Description 0x000000000x1FFFFFFF Code Normal (1) - Executable region for program code. You can also put data here. - Executable region for data. You can also put code here.
Table 10-5. Memory region share ability policies (Continued) Address range Memory region 0xA00000000xBFFFFFFF Memory type Shareable (1) External device Device (1) 0xC00000000xDFFFFFFF 10.5.4 Shareability Nonshareable (1) 0xE00000000xE00FFFFF Private Peripheral Bus Stronglyordered(1) Shareable (1) - 0xE01000000xFFFFFFFF Vendor-specific device(2) Device (1) - - 1. See “Memory regions, types and attributes” on page 55 for more information. 2.
SAM3N • Memory map switching. If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. This ensures subsequent instruction execution uses the updated memory map. • Dynamic exception priority change. When an exception priority has to change when the exception is pending or active, use DSB instructions after the change. This ensures the change takes effect on completion of the DSB instruction. • Using a semaphore in multi-master system.
bit_word_addr = bit_band_base + bit_word_offset where: • Bit_word_offset is the position of the target bit in the bit-band memory region. • Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. • Bit_band_base is the starting address of the alias region. • Byte_offset is the number of the byte in the bit-band region that contains the targeted bit. • Bit_number is the bit position, 0-7, of the targeted bit.
SAM3N Reading a word in the alias region: • 0x00000000 indicates that the targeted bit in the bit-band region is set to zero • 0x00000001 indicates that the targeted bit in the bit-band region is set to 1 10.5.5.2 10.5.6 10.5.6.1 Directly accessing a bit-band region “Behavior of memory accesses” on page 57 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions.
• the halfword instructions LDREXH and STREXH • the byte instructions LDREXB and STREXB. Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform a guaranteed read-modify-write of a memory location, software must: • Use a Load-Exclusive instruction to read the value of the location. • Update the value, as required. • Use a Store-Exclusive instruction to attempt to write the new value back to the memory location, and tests the returned status bit.
SAM3N 10.5.8 Programming hints for the synchronization primitives ANSI C cannot directly generate the exclusive access instructions. Some C compilers provide intrinsic functions for generation of these instructions: Table 10-8.
vided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. 10.6.2.2 Non Maskable Interrupt (NMI) A non maskable interrupt (NMI) can be signalled by a peripheral or triggered by software. This is the highest priority exception other than reset. It is permanently enabled and has a fixed priority of -2. NMIs cannot be: • Masked or prevented from activation by any other exception. • Preempted by any exception other than Reset. 10.6.2.
SAM3N 10.6.2.9 Interrupt (IRQ) A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 10-9.
• “Interrupt Clear-enable Registers” on page 154. For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault handling” on page 70. 10.6.3 Exception handlers The processor handles exceptions using: 10.6.3.1 Interrupt Service Routines (ISRs) Interrupts IRQ0 to IRQ32 are the exceptions handled by ISRs. 10.6.3.2 Fault handlers Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault handlers. 10.6.3.
SAM3N Figure 10-3. Vector table Exception number IRQ number 45 29 . . . 18 2 17 1 16 0 15 -1 14 -2 13 Offset 0x00B4 . . . 0x004C 0x0048 0x0044 0x0040 0x003C 0x0038 IRQ29 . . .
Configurable priority values are in the range 0-15. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].
SAM3N 10.6.7.3 Tail-chaining This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. 10.6.7.4 Late-arriving This mechanism speeds up preemption.
If no higher priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher priority exception occurs during exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case. 10.6.7.
SAM3N • an internally-detected error such as an undefined instruction or an attempt to change state with a BX instruction • attempting to execute an instruction from a memory region marked as Non-Executable (XN). 10.7.1 Fault types Table 10-11 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates that the fault has occurred.
• A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is because the handler for the new fault cannot preempt the currently executing fault handler. • An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. • A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault.
SAM3N The SLEEPDEEP bit of the SCR selects which sleep mode is used, see “System Control Register” on page 173. For more information about the behavior of the sleep modes see “Low Power Modes” in the PMC section of the datasheet. This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode. 10.8.1 Entering sleep mode This section describes the mechanisms software can use to put the processor into sleep mode.
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about the SCR see “System Control Register” on page 173. 10.8.3 Power management programming hints ANSI C cannot directly generate the WFI and WFE instructions.
SAM3N 10.9 Instruction set summary The processor implements a version of the Thumb instruction set. Table 10-13 lists the supported instructions. In Table 10-13: • angle brackets, <>, enclose alternative forms of the operand • braces, {}, enclose optional operands • the Operands column is not exhaustive • Op2 is a flexible second operand that can be either a register or a constant • most instructions can use an optional condition code suffix.
Table 10-13.
SAM3N Table 10-13.
Table 10-13.
SAM3N The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions: Table 10-15.
Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M3 processor only supports Thumb instructions. 10.11.3 Flexible second operand Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the descriptions of the syntax of each instruction. Operand2 can be a: • “Constant” • “Register with optional shift” on page 80 10.11.
SAM3N LSR #n logical shift right n bits, 1 ≤n ≤32. ROR #n rotate right n bits, 1 ≤n ≤31. RRX rotate right one bit, with extend. - if omitted, no shift occurs, equivalent to LSL #0. If you omit the shift, or specify LSL #0, the instruction uses the value in Rm. If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the instruction. However, the contents in the register Rm remains unchanged.
10.11.4.2 LSR Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 10-5. You can use the LSR #n operation to divide the value in the register Rm by 2n, if the value is regarded as an unsigned integer.
SAM3N 10.11.4.4 ROR Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it moves the right-hand n bits of the register into the left-hand n bits of the result. See Figure 10-7. When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1], of the register Rm.
All other load and store instructions generate a usage fault exception if they perform an unaligned access, and therefore their accesses must be address aligned. For more information about usage faults see “Fault handling” on page 70. Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned.
SAM3N This section describes: • “The condition flags” • “Condition code suffixes” . 10.11.7.1 The condition flags The APSR contains the following condition flags: N Set to 1 when the result of the operation was negative, cleared to 0 otherwise. Z Set to 1 when the result of the operation was zero, cleared to 0 otherwise. C Set to 1 when the operation resulted in a carry, cleared to 0 otherwise. V Set to 1 when the operation caused overflow, cleared to 0 otherwise.
Table 10-16. Condition code suffixes (Continued) Suffix Flags Meaning VC V=0 No overflow HI C = 1 and Z = 0 Higher, unsigned > LS C = 0 or Z = 1 Lower or same, unsigned ≤ GE N=V Greater than or equal, signed ≥ LT N! =V Less than, signed < GT Z = 0 and N = V Greater than, signed > LE Z = 1 and N ! = V Less than or equal, signed ≤ AL Can have any value Always. This is the default when no suffix is specified. 10.11.7.
SAM3N 10.12 Memory access instructions Table 10-17 shows the memory access instructions: Table 10-17.
10.12.1 ADR Load PC-relative address. 10.12.1.1 Syntax ADR{cond} Rd, label where: 10.12.1.2 cond is an optional condition code, see “Conditional execution” on page 84. Rd is the destination register. label is a PC-relative expression. See “PC-relative expressions” on page 84. Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, because the address is PC-relative.
SAM3N 10.12.2 10.12.2.1 LDR and STR, immediate offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.
[Rn, #offset]! 10.12.2.5 Post-indexed addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for this mode is: [Rn], #offset The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned. See “Address alignment” on page 83.
SAM3N 10.12.2.8 Examples LDR LDRNE R8, [R10] R2, [R5, #960]! STR R2, [R9,#const-struc] STRH R3, [R4], #4 LDRD R8, R9, [R3, #0x20] STRD R0, R1, [R8], #-16 ; ; ; ; ; ; ; ; ; ; ; ; ; ; Loads R8 from the address in R10. Loads (conditionally) R2 from a word 960 bytes above the address in R5, and increments R5 by 960. const-struc is an expression evaluating to a constant in the range 0-4095.
10.12.3 10.12.3.1 LDR and STR, register offset Load and Store with register offset. Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}] where: op is one of: LDR Load Register. STR Store Register. type 10.12.3.2 is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word.
SAM3N 10.12.3.4 Condition flags These instructions do not change the flags. 10.12.3.
10.12.4 LDR and STR, unprivileged Load and Store with unprivileged access. 10.12.4.1 Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word.
SAM3N 10.12.5 10.12.5.1 LDR, PC-relative Load register from memory. Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label ; Load two words where: type 10.12.5.2 is one of: B unsigned byte, zero extend to 32 bits. SB signed byte, sign extend to 32 bits. H unsigned halfword, zero extend to 32 bits. SH signed halfword, sign extend to 32 bits. - omit, for word. cond is an optional condition code, see “Conditional execution” on page 84. Rt is the register to load or store.
• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address • if the instruction is conditional, it must be the last instruction in the IT block. 10.12.5.4 Condition flags These instructions do not change the flags. 10.12.5.
SAM3N 10.12.6 LDM and STM Load and Store Multiple registers. 10.12.6.1 Syntax op{addr_mode}{cond} Rn{!}, reglist where: op is one of: LDM Load Multiple registers. STM Store Multiple registers. addr_mode is any one of the following: IA Increment address After each access. This is the default. DB Decrement address Before each access. cond is an optional condition code, see “Conditional execution” on page 84. Rn is the register on which the memory addresses are based.
The accesses happen in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn. The PUSH and POP instructions can be expressed in this form. See “PUSH and POP” on page 99 for details. 10.12.6.
SAM3N 10.12.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. 10.12.7.1 Syntax PUSH{cond} reglist POP{cond} reglist where: cond is an optional condition code, see “Conditional execution” on page 84. reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range.
10.12.8 10.12.8.1 LDREX and STREX Load and Store Register Exclusive. Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond is an optional condition code, see “Conditional execution” on page 84. Rd is the destination register for the returned status. Rt is the register to load or store. Rn is the register on which the memory address is based.
SAM3N 10.12.8.4 Condition flags These instructions do not change the flags. 10.12.8.5 Examples MOV R1, #0x1 ; Initialize the ‘lock taken’ value LDREX CMP ITT STREXEQ CMPEQ BNE ....
10.12.9 CLREX Clear Exclusive. 10.12.9.1 Syntax CLREX{cond} where: cond 10.12.9.2 is an optional condition code, see “Conditional execution” on page 84. Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to perform the store.
SAM3N 10.13 General data processing instructions Table 10-20 shows the data processing instructions: Table 10-20.
Table 10-20.
SAM3N 10.13.1 10.13.1.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only where: op is one of: ADD Add. ADC Add with Carry. SUB Subtract. SBC Subtract with Carry. RSB Reverse Subtract. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 84.
• Rd can be SP only in ADD and SUB, and only with the additional restrictions: – Rn must also be SP – any shift in Operand2 must be limited to a maximum of 3 bits using LSL • Rn can be SP only in ADD and SUB • Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where: – you must not specify the S suffix – Rm must not be PC and must not be SP – if the instruction is conditional, it must be the last instruction in the IT block • with the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC on
SAM3N 10.13.1.6 Multiword arithmetic examples 10.13.1.7 64-bit addition The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5. ADDS ADC R4, R0, R2 R5, R1, R3 ; add the least significant words ; add the most significant words with carry 10.13.1.8 96-bit subtraction Multiword values do not have to use consecutive registers.
10.13.2 10.13.2.1 AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. Syntax op{S}{cond} {Rd,} Rn, Operand2 where: op is one of: AND logical AND. ORR logical OR, or bit set. EOR logical Exclusive OR. BIC logical AND NOT, or bit clear. ORN logical OR NOT. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 84.
SAM3N 10.13.2.
10.13.3 10.13.3.1 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: op is one of: ASR Arithmetic Shift Right. LSL Logical Shift Left. LSR Logical Shift Right. ROR Rotate Right. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 84.
SAM3N • the C flag is updated to the last bit shifted out, except when the shift length is 0, see “Shift Operations” on page 81. 10.13.3.
10.13.4 CLZ Count Leading Zeros. 10.13.4.1 Syntax CLZ{cond} Rd, Rm where: 10.13.4.2 cond is an optional condition code, see “Conditional execution” on page 84. Rd is the destination register. Rm is the operand register. Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result value is 32 if no bits are set in the source register, and zero if bit[31] is set. 10.13.4.3 Restrictions Do not use SP and do not use PC. 10.13.4.
SAM3N 10.13.5 CMP and CMN Compare and Compare Negative. 10.13.5.1 Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see “Conditional execution” on page 84. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible second operand” on page 80 for details of the options. 10.13.5.2 Operation These instructions compare the value in a register with Operand2.
10.13.6 MOV and MVN Move and Move NOT. 10.13.6.1 Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 84. cond is an optional condition code, see “Conditional execution” on page 84. Rd is the destination register. Operand2 is a flexible second operand. See “Flexible second operand” on page 80 for details of the options.
SAM3N • bit[0] of the value written to the PC is ignored • a branch occurs to the address created by forcing bit[0] of that value to 0. Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX instruction to branch for software portability to the ARM instruction set. 10.13.6.
10.13.7 MOVT Move Top. 10.13.7.1 Syntax MOVT{cond} Rd, #imm16 where: 10.13.7.2 cond is an optional condition code, see “Conditional execution” on page 84. Rd is the destination register. imm16 is a 16-bit immediate constant. Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does not affect Rd[15:0]. The MOV, MOVT instruction pair enables you to generate any 32-bit constant. 10.13.7.
SAM3N 10.13.8 REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. 10.13.8.1 Syntax op{cond} Rd, Rn where: op is any of: REV Reverse byte order in a word. REV16 Reverse byte order in each halfword independently. REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits. RBIT 10.13.8.2 Reverse the bit order in a 32-bit word. cond is an optional condition code, see “Conditional execution” on page 84. Rd is the destination register.
10.13.9 TST and TEQ Test bits and Test Equivalence. 10.13.9.1 Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where: cond is an optional condition code, see “Conditional execution” on page 84. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible second operand” on page 80 for details of the options. 10.13.9.2 Operation These instructions test the value in a register against Operand2.
SAM3N 10.14 Multiply and divide instructions Table 10-21 shows the multiply and divide instructions: Table 10-21.
10.14.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. 10.14.1.1 Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract where: cond is an optional condition code, see “Conditional execution” on page 84. S is an optional suffix.
SAM3N 10.14.2 UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. 10.14.2.1 Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL Unsigned Long Multiply. UMLAL Unsigned Long Multiply, with Accumulate. SMULL Signed Long Multiply. SMLAL Signed Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional execution” on page 84. RdHi, RdLo are the destination registers.
10.14.3 SDIV and UDIV Signed Divide and Unsigned Divide. 10.14.3.1 Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: 10.14.3.2 cond is an optional condition code, see “Conditional execution” on page 84. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the value to be divided. Rm is a register holding the divisor. Operation SDIV performs a signed integer division of the value in Rn by the value in Rm.
SAM3N 10.15 Saturating instructions This section describes the saturating instructions, SSAT and USAT. 10.15.1 10.15.1.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. Syntax op{cond} Rd, #n, Rm {, shift #s} where: op is one of: SSAT Saturates a signed value to a signed range. USAT Saturates a signed value to an unsigned range. cond is an optional condition code, see “Conditional execution” on page 84.
10.15.1.3 Restrictions Do not use SP and do not use PC. 10.15.1.4 Condition flags These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1. 10.15.1.
SAM3N 10.16 Bitfield instructions Table 10-22 shows the instructions that operate on adjacent sets of bits in registers or bitfields: Table 10-22.
10.16.1 BFC and BFI Bit Field Clear and Bit Field Insert. 10.16.1.1 Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional execution” on page 84. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width 10.16.1.2 is the width of the bitfield and must be in the range 1 to 32−lsb.
SAM3N 10.16.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. 10.16.2.1 Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional execution” on page 84. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width 10.16.2.2 is the width of the bitfield and must be in the range 1 to 32−lsb.
10.16.3 SXT and UXT Sign extend and Zero extend. 10.16.3.1 Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: B Extends an 8-bit value to a 32-bit value. H Extends a 16-bit value to a 32-bit value. cond is an optional condition code, see “Conditional execution” on page 84. Rd is the destination register. Rm is the register holding the value to extend. ROR #n is one of: ROR #8 Value from Rm is rotated right 8 bits.
SAM3N 10.17 Branch and control instructions Table 10-23 shows the branch and control instructions: Table 10-23.
10.17.1 10.17.1.1 B, BL, BX, and BLX Branch instructions. Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: B is branch (immediate). BL is branch with link (immediate). BX is branch indirect (register). BLX is branch indirect with link (register). cond is an optional condition code, see “Conditional execution” on page 84. label is a PC-relative expression. See “PC-relative expressions” on page 84. Rm is a register that indicates an address to branch to.
SAM3N • do not use PC in the BLX instruction • for BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address created by changing bit[0] to 0 • when any of these instructions is inside an IT block, it must be the last instruction of the IT block. Bcond is the only conditional instruction that is not required to be inside an IT block. However, it has a longer branch range when it is inside an IT block. 10.17.1.
10.17.2 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. 10.17.2.1 Syntax CBZ Rn, label CBNZ Rn, label where: 10.17.2.2 Rn is the register holding the operand. label is the branch destination. Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions.
SAM3N 10.17.3 IT If-Then condition instruction. 10.17.3.1 Syntax IT{x{y{z}}} cond where: x specifies the condition switch for the second instruction in the IT block. y specifies the condition switch for the third instruction in the IT block. z specifies the condition switch for the fourth instruction in the IT block. cond specifies the condition for the first instruction in the IT block. The condition switch for the second, third and fourth instruction in the IT block can be either: T Then.
• a branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction inside the IT block. These are: – ADD PC, PC, Rm – MOV PC, Rm – B, BL, BX, BLX – any LDM, LDR, or POP instruction that writes to the PC – TBB and TBH • do not branch to any instruction inside an IT block, except when returning from an exception handler • all conditional instructions except Bcond must be inside an IT block.
SAM3N 10.17.4 TBB and TBH Table Branch Byte and Table Branch Halfword. 10.17.4.1 Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: Rn is the register containing the address of the table of branch lengths. If Rn is PC, then the address of the table is the address of the byte immediately following the TBB or TBH instruction. Rm is the index register. This contains an index into the table. For halfword tables, LSL #1 doubles the value in Rm to form the right offset into the table. 10.17.4.
10.17.4.5 Examples ADR.
SAM3N 10.18 Miscellaneous instructions Table 10-25 shows the remaining Cortex-M3 instructions: Table 10-25.
10.18.1 BKPT Breakpoint. 10.18.1.1 Syntax BKPT #imm where: imm 10.18.1.2 is an expression evaluating to an integer in the range 0-255 (8-bit value). Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.
SAM3N 10.18.2 CPS Change Processor State. 10.18.2.1 Syntax CPSeffect iflags where: effect is one of: IE Clears the special purpose register. ID Sets the special purpose register. iflags 10.18.2.2 is a sequence of one or more flags: i Set or clear PRIMASK. f Set or clear FAULTMASK. Operation CPS changes the PRIMASK and FAULTMASK special register values. See “Exception mask registers” on page 49 for more information about these registers. 10.18.2.
10.18.3 DMB Data Memory Barrier. 10.18.3.1 Syntax DMB{cond} where: cond 10.18.3.2 is an optional condition code, see “Conditional execution” on page 84. Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access memory. 10.18.
SAM3N 10.18.4 DSB Data Synchronization Barrier. 10.18.4.1 Syntax DSB{cond} where: cond 10.18.4.2 is an optional condition code, see “Conditional execution” on page 84. Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete. 10.18.4.3 Condition flags This instruction does not change the flags. 10.
10.18.5 ISB Instruction Synchronization Barrier. 10.18.5.1 Syntax ISB{cond} where: cond 10.18.5.2 is an optional condition code, see “Conditional execution” on page 84. Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from memory again, after the ISB instruction has been completed. 10.18.5.3 Condition flags This instruction does not change the flags. 10.18.5.
SAM3N 10.18.6 MRS Move the contents of a special register to a general-purpose register. 10.18.6.1 Syntax MRS{cond} Rd, spec_reg where: cond is an optional condition code, see “Conditional execution” on page 84. Rd is the destination register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. 10.18.6.
10.18.7 MSR Move the contents of a general-purpose register into the specified special register. 10.18.7.1 Syntax MSR{cond} spec_reg, Rn where: cond is an optional condition code, see “Conditional execution” on page 84. Rn is the source register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. 10.18.7.2 Operation The register access operation in MSR depends on the privilege level.
SAM3N 10.18.8 NOP No Operation. 10.18.8.1 Syntax NOP{cond} where: cond 10.18.8.2 is an optional condition code, see “Conditional execution” on page 84. Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for example to place the following instruction on a 64-bit boundary. 10.18.8.3 Condition flags This instruction does not change the flags. 10.18.8.
10.18.9 SEV Send Event. 10.18.9.1 Syntax SEV{cond} where: cond 10.18.9.2 is an optional condition code, see “Conditional execution” on page 84. Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It also sets the local event register to 1, see “Power management” on page 72. 10.18.9.3 Condition flags This instruction does not change the flags. 10.18.9.
SAM3N 10.18.10 SVC Supervisor Call. 10.18.10.1 Syntax SVC{cond} #imm where: 10.18.10.2 cond is an optional condition code, see “Conditional execution” on page 84. imm is an expression evaluating to an integer in the range 0-255 (8-bit value). Operation The SVC instruction causes the SVC exception. imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service is being requested. 10.18.10.
10.18.11 WFE Wait For Event. 10.18.11.1 Syntax WFE{cond} where: cond 10.18.11.2 is an optional condition code, see “Conditional execution” on page 84. Operation WFE is a hint instruction.
SAM3N 10.18.12 WFI Wait for Interrupt. 10.18.12.1 Syntax WFI{cond} where: cond 10.18.12.2 is an optional condition code, see “Conditional execution” on page 84. Operation WFI is a hint instruction that suspends execution until one of the following events occurs: • an exception • a Debug Entry request, regardless of whether Debug is enabled. 10.18.12.3 Condition flags This instruction does not change the flags. 10.18.12.
10.19 About the Cortex-M3 peripherals The address map of the Private peripheral bus (PPB) is: Table 10-26.
SAM3N 10.20 Nested Vectored Interrupt Controller This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: • 1 to 33 interrupts. • A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. • Level and pulse detection of interrupt signals. • Dynamic reprioritization of interrupts. • Grouping of priority values into group priority and subpriority fields.
• the 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the array IP[0] to IP[32] corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds the interrupt priority for interrupt n. The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. For more information see the description of the NVIC_SetPriority function in “NVIC programming hints” on page 163.
SAM3N 10.20.2 Interrupt Set-enable Registers The ISER0 register enables interrupts, and show which interrupts are enabled. See: • the register summary in Table 10-27 on page 151 for the register attributes • Table 10-28 on page 152 for which interrupts are controlled by each register.
10.20.3 Interrupt Clear-enable Registers The ICER0 register disables interrupts, and shows which interrupts are enabled. See: • the register summary in Table 10-27 on page 151 for the register attributes • Table 10-28 on page 152 for which interrupts are controlled by each register The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRENA 23 22 21 20 CLRENA 15 14 13 12 CLRENA 7 6 5 4 CLRENA • CLRENA Interrupt clear-enable bits.
SAM3N 10.20.4 Interrupt Set-pending Registers The ISPR0 register forces interrupts into the pending state, and shows which interrupts are pending. See: • the register summary in Table 10-27 on page 151 for the register attributes • Table 10-28 on page 152 for which interrupts are controlled by each register.
10.20.5 Interrupt Clear-pending Registers The ICPR0 register removes the pending state from interrupts, and show which interrupts are pending. See: • the register summary in Table 10-27 on page 151 for the register attributes • Table 10-28 on page 152 for which interrupts are controlled by each register.
SAM3N 10.20.6 Interrupt Active Bit Registers The IABR0 register indicates which interrupts are active. See: • the register summary in Table 10-27 on page 151 for the register attributes • Table 10-28 on page 152 for which interrupts are controlled by each register.
10.20.7 10.20.7.1 Interrupt Priority Registers The IPR0-IPR8 registers provide a 4-bit priority field for each interrupt (See the “Peripheral Identifiers” section of the datasheet for more details). These registers are byte-accessible. See the register summary in Table 10-27 on page 151 for their attributes.
SAM3N 10.20.7.4 IPR2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IP[11] 23 22 21 20 IP[10] 15 14 13 12 IP[9] 7 6 5 4 IP[8] 10.20.7.5 IPR1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IP[6] 15 14 13 12 IP[5] 7 6 5 4 IP[4] 10.20.7.
Find the IPR number and byte offset for interrupt N as follows: • the corresponding IPR number, M, is given by M = N DIV 4 • the byte offset of the required Priority field in this register is N MOD 4, where: – byte offset 0 refers to register bits[7:0] – byte offset 1 refers to register bits[15:8] – byte offset 2 refers to register bits[23:16] – byte offset 3 refers to register bits[31:24].
SAM3N 10.20.8 Software Trigger Interrupt Register Write to the STIR to generate a Software Generated Interrupt (SGI). See the register summary in Table 10-27 on page 151 for the STIR attributes. When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR, see “System Control Register” on page 173. Only privileged software can enable unprivileged access to the STIR.
10.20.9 Level-sensitive interrupts The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. When the processor enters the ISR, it automatically removes the pending state from the interrupt, see “Hardware and software control of interrupts” .
SAM3N 10.20.10 NVIC design hints and tips Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. See the individual register descriptions for the supported access sizes. A interrupt can enter pending state even it is disabled. Before programming VTOR to relocate the vector table, ensure the vector table entries of the new vector table are setup for fault handlers and all enabled exception like interrupts.
10.21 System control block The System control block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. The system control block registers are: Table 10-30.
SAM3N 10.21.2 Auxiliary Control Register The ACTLR provides disable bits for the following processor functions: • IT folding • write buffer use for accesses to the default memory map • interruption of multi-cycle instructions. See the register summary in Table 10-30 on page 164 for the ACTLR attributes.
10.21.3 CPUID Base Register The CPUID register contains the processor part number, version, and implementation information. See the register summary in Table 10-30 on page 164 for its attributes.
SAM3N 10.21.4 Interrupt Control and State Register The ICSR: • provides: – set-pending and clear-pending bits for the PendSV and SysTick exceptions • indicates: – the exception number of the exception being processed – whether there are preempted active exceptions – the exception number of the highest priority pending exception – whether any interrupts are pending. See the register summary in Table 10-30 on page 164, and the Type descriptions in Table 10-33 on page 191, for the ICSR attributes.
• PENDSTSET RW SysTick exception set-pending bit. Write: 0 = no effect 1 = changes SysTick exception state to pending. Read: 0 = SysTick exception is not pending 1 = SysTick exception is pending. • PENDSTCLR WO SysTick exception clear-pending bit. Write: 0 = no effect 1 = removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown. • Reserved for Debug use RO This bit is reserved for Debug use and reads-as-zero when the processor is not in Debug.
SAM3N • RETTOBASE RO Indicates whether there are preempted active exceptions: 0 = there are preempted active exceptions to execute 1 = there are no active exceptions, or the currently-executing exception is the only active exception. • VECTACTIVE RO Contains the active exception number: 0 = Thread mode Nonzero = The exception number (1) of the currently active exception.
10.21.5 Vector Table Offset Register The VTOR indicates the offset of the vector table base address from memory address 0x00000000. See the register summary in Table 10-30 on page 164 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 TBLOFF 22 21 20 TBLOFF 15 14 13 12 TBLOFF 7 6 5 TBLOFF 4 Reserved • TBLOFF Vector table base offset field.
SAM3N 10.21.6 Application Interrupt and Reset Control Register The AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. See the register summary in Table 10-30 on page 164 and Table 10-33 on page 191 for its attributes. To write to this register, you must write 0x05FA to the VECTKEY field, otherwise the processor ignores the write.
• VECTCLRACTIVE WO Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. • VECTRESET WO Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. 10.21.6.
SAM3N 10.21.7 System Control Register The SCR controls features of entry to and exit from low power state. See the register summary in Table 10-30 on page 164 for its attributes.
10.21.8 Configuration and Control Register The CCR controls entry to Thread mode and enables: • the handlers for hard fault and faults escalated by FAULTMASK to ignore bus faults • trapping of divide by zero and unaligned accesses • access to the STIR by unprivileged software, see “Software Trigger Interrupt Register” on page 161. See the register summary in Table 10-30 on page 164 for the CCR attributes.
SAM3N 1 = trap unaligned halfword and word accesses. If this bit is set to 1, an unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1. • USERSETMPEND Enables unprivileged software access to the STIR, see “Software Trigger Interrupt Register” on page 161: 0 = disable 1 = enable. • NONEBASETHRDENA Indicates how the processor enters Thread mode: 0 = processor can enter Thread mode only when no exception is active.
10.21.9 System Handler Priority Registers The SHPR1-SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority. SHPR1-SHPR3 are byte accessible. See the register summary in Table 10-30 on page 164 for their attributes. The system fault handlers and the priority field and register for each handler are: Table 10-32.
SAM3N 10.21.9.
10.21.9.2 31 System Handler Priority Register 2 The bit assignments are: 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI_11 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved • PRI_11 Priority of system handler 11, SVCall 10.21.9.
SAM3N 10.21.10 System Handler Control and State Register The SHCSR enables the system handlers, and indicates: • the pending status of the bus fault, memory management fault, and SVC exceptions • the active status of the system handlers. See the register summary in Table 10-30 on page 164 for the SHCSR attributes.
• MONITORACT Debug monitor active bit, reads as 1 if Debug monitor is active • SVCALLACT SVC call active bit, reads as 1 if SVC call is active • USGFAULTACT Usage fault exception active bit, reads as 1 if exception is active • BUSFAULTACT Bus fault exception active bit, reads as 1 if exception is active • MEMFAULTACT Memory management fault exception active bit, reads as 1 if exception is active If you disable a system handler and the corresponding fault occurs, the processor treats the fault as a hard fau
SAM3N 10.21.11 Configurable Fault Status Register The CFSR indicates the cause of a memory management fault, bus fault, or usage fault. See the register summary in Table 10-30 on page 164 for its attributes.
10.21.11.1 Memory Management Fault Status Register The flags in the MMFSR indicate the cause of memory access faults. The bit assignments are: 7 6 MMARVALID 5 Reserved 4 3 2 1 0 MSTKERR MUNSTKERR Reserved DACCVIOL IACCVIOL • MMARVALID Memory Management Fault Address Register (MMAR) valid flag: 0 = value in MMAR is not a valid fault address 1 = MMAR holds a valid fault address.
SAM3N 10.21.11.2 Bus Fault Status Register The flags in the BFSR indicate the cause of a bus access fault. The bit assignments are: 7 6 BFRVALID 5 Reserved 4 3 2 1 0 STKERR UNSTKERR IMPRECISERR PRECISERR IBUSERR • BFARVALID Bus Fault Address Register (BFAR) valid flag: 0 = value in BFAR is not a valid fault address 1 = BFAR holds a valid fault address. The processor sets this bit to 1 after a bus fault where the address is known.
• PRECISERR Precise data bus error: 0 = no precise data bus error 1 = a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When the processor sets this bit is 1, it writes the faulting address to the BFAR. • IBUSERR Instruction bus error: 0 = no instruction bus error 1 = instruction bus error.
SAM3N 10.21.11.3 Usage Fault Status Register The UFSR indicates the cause of a usage fault. The bit assignments are: 15 14 13 12 11 10 Reserved 7 6 5 4 Reserved 9 8 DIVBYZERO UNALIGNED 3 2 1 0 NOCP INVPC INVSTATE UNDEFINSTR • DIVBYZERO Divide by zero usage fault: 0 = no divide by zero fault, or divide by zero trapping not enabled 1 = the processor has executed an SDIV or UDIV instruction with a divisor of 0.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the EPSR. This bit is not set to 1 if an undefined instruction uses the EPSR. • UNDEFINSTR Undefined instruction usage fault: 0 = no undefined instruction usage fault 1 = the processor has attempted to execute an undefined instruction. When this bit is set to 1, the PC value stacked for the exception return points to the undefined instruction.
SAM3N 10.21.12 Hard Fault Status Register The HFSR gives information about events that activate the hard fault handler. See the register summary in Table 10-30 on page 164 for its attributes. This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0.
10.21.13 Memory Management Fault Address Register The MMFAR contains the address of the location that generated a memory management fault. See the register summary in Table 10-30 on page 164 for its attributes.
SAM3N 10.21.14 Bus Fault Address Register The BFAR contains the address of the location that generated a bus fault. See the register summary in Table 10-30 on page 164 for its attributes.
10.21.15 System control block design hints and tips Ensure software uses aligned accesses of the correct size to access the system control block registers: • except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses • for the CFSR and SHPR1-SHPR3 it can use byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. In a fault handler. to determine the true faulting address: • Read and save the MMFAR or BFAR value.
SAM3N 10.22 System timer, SysTick The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the LOAD register on the next clock edge, then counts down on subsequent clocks. When the processor is halted for debugging the counter does not decrement. The system timer registers are: Table 10-33.
10.22.1 SysTick Control and Status Register The SysTick CTRL register enables the SysTick features. See the register summary in Table 1033 on page 191 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 19 18 17 24 Reserved 23 22 21 20 16 Reserved 15 14 13 12 COUNTFLAG 11 10 9 8 Reserved 7 6 5 4 3 Reserved 2 1 0 CLKSOURCE TICKINT ENABLE • COUNTFLAG Returns 1 if timer counted to 0 since last time this was read.
SAM3N 10.22.2 SysTick Reload Value Register The LOAD register specifies the start value to load into the VAL register. See the register summary in Table 10-33 on page 191 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 RELOAD 15 14 13 12 RELOAD 7 6 5 4 -RELOAD • RELOAD Value to load into the VAL register when the counter is enabled and when it reaches 0, see “Calculating the RELOAD value” . 10.22.2.
10.22.3 31 SysTick Current Value Register The VAL register contains the current value of the SysTick counter. See the register summary in Table 10-33 on page 191 for its attributes. The bit assignments are: 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 CURRENT 15 14 13 12 CURRENT 7 6 5 4 CURRENT • CURRENT Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SysTick CTRL.
SAM3N 10.22.4 SysTick Calibration Value Register The CALIB register indicates the SysTick calibration properties. See the register summary in Table 10-33 on page 191 for its attributes. The bit assignments are: 31 30 NOREF SKEW 23 22 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 21 20 TENMS 15 14 13 12 TENMS 7 6 5 4 TENMS • NOREF Reads as zero. • SKEW Reads as zero • TENMS Read as 0x0002904.
10.23 Glossary This glossary describes some of the terms used in technical documents from ARM. Abort A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned.
SAM3N Debugger A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging. Direct Memory Access (DMA) An operation that accesses main memory directly, without the processor performing any accesses to the data concerned. Doubleword A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated. Doubleword-aligned A data item having a memory address that is divisible by eight.
The behavior is not architecturally defined, and does not have to be documented by individual implementations. Used when there are a number of implementation options available and the option chosen does not affect software compatibility. Index register In some load and store instruction descriptions, the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to memory.
SAM3N Region A partition of memory space. Reserved A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces Unpredictable results if the contents of the field are not zero. These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as 0 and read as 0. Should Be One (SBO) Write as 1, or all 1s for bit fields, by software.
SAM3N 11011B–ATARM–21-Feb-12
SAM3N 11. Debug and Test Features 11.1 Description The SAM3 Series Microcontrollers feature a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug(JTAG-DP) port is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace. 11.
11.3 11.3.1 Application Examples Debug Environment Figure 11-2 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers. Figure 11-2. Application Debug Environment Example Host Debugger PC SWJ-DP Emulator/Probe SWJ-DP Connector SAM3 SAM3-based Application Board 11.3.
SAM3N Figure 11-3. Application Test Environment Example Test Adaptor Tester JTAG Probe JTAG Connector Chip n SAM3 Chip 2 Chip 1 SAM3-based Application Board In Test 11.4 Debug and Test Pin Description Table 11-1.
11.5 11.5.1 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during power-up, the device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST pin integrates a permanent pull-down resistor of about 15 kΩ, so that it can be left unconnected for normal operation.
SAM3N When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP. Table 11-2. SWJ-DP Pin List Pin Name JTAG Port Serial Wire Debug Port TMS/SWDIO TMS SWDIO TCK/SWCLK TCK SWCLK TDI TDI - TDO/TRACESWO TDO TRACESWO (optional: trace) SW-DP or JTAG-DP mode is selected when JTAGSEL is low.
• Watchpoint event to halt core The DWT contains counters for the items that follow: • Clock cycle (CYCCNT) • Folded instructions • Load Store Unit (LSU) operations • Sleep Cycles • CPI (all instruction cycles except for the first cycle) • Interrupt overhead 11.5.6 ITM (Instrumentation Trace Macrocell) The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information.
SAM3N 11.5.6.2 Asynchronous Mode The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Port. As a consequence, asynchronous trace mode is only available when the Serial Wire Debug mode is selected since TDO signal is used in JTAG debug mode. Two encoding formats are available for the single pin output: • Manchester encoded stream. This is the reset value. • NRZ_based UART byte structure 11.
11.5.8 ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 0 MANUFACTURER IDENTITY 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name Chip ID SAM3N 0x05B2E • MANUFACTURER IDENTITY[11:1] Set to 0x01F. • Bit[0] Required by IEEE Std. 1149.1. Set to 0x1.
SAM3N 12. Reset Controller (RSTC) 12.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 12.2 Embedded Characteristics The Reset Controller is based on a Power-on-Reset cell, and a Supply Monitor on VDDCORE.
12.4 Functional Description 12.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset line. It also resets the Watchdog Timer. • periph_nreset: Affects the whole set of embedded peripherals. • nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action.
The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. 12.4.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles.
Figure 12-3. General Reset State SLCK Any Freq. MCK backup_nreset Processor Startup = 2 cycles proc_nreset RSTTYP XXX 0x0 = General Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles 12.4.4.2 Backup Reset A Backup reset occurs when the chip returns from Backup mode. The core_backup_reset signal is asserted by the Supply Controller when a Backup reset occurs. The field RSTTYP in RSTC_SR is updated to report a Backup Reset. 12.4.4.
Figure 12-4. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 2 cycles proc_nreset RSTTYP Any XXX 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL RESET LENGTH 12.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals.
No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 12-5. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. Processor Startup 1 cycle = 2 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 12.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs.
Figure 12-6. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 2 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 12.4.
12.4.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
12.5 Reset Controller (RSTC) User Interface Table 12-1.
12.5.1 Name: Reset Controller Control Register RSTC_CR Address: 0x400E1400 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect.
12.5.2 Name: Reset Controller Status Register RSTC_SR Address: 0x400E1404 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
12.5.3 Name: Reset Controller Mode Register RSTC_MR Address: 0x400E1408 Access: Read-write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset.
SAM3N 13. Real-time Timer (RTT) 13.1 Description The Real-time Timer is built around a 32-bit counter used to count roll-over events of the programmable16-bit prescaler which enables counting elapsed seconds from a 32 kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 13.2 Embedded Characteristics • 32-bit Free-running Counter on prescaled slow clock • 16-bit Configurable Prescaler • Interrupt on Alarm 13.3 Block Diagram Figure 13-1.
13.4 Functional Description The Real-time Timer can be used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0.
SAM3N Figure 13-2. RTT Counting APB cycle APB cycle SCLK RTPRES - 1 Prescaler 0 RTT 0 ...
13.5 Real-time Timer (RTT) User Interface Table 13-1.
SAM3N 13.5.1 Real-time Timer Mode Register Register Name: RTT_MR Address: 0x400E1430 Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216 * SCLK period.
13.5.2 Real-time Timer Alarm Register Register Name: RTT_AR Address: 0x400E1434 Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer.
SAM3N 13.5.3 Real-time Timer Value Register Register Name: RTT_VR Address: 0x400E1438 Access Type: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV • CRTV: Current Real-time Value Returns the current value of the Real-time Timer.
SAM3N 13.5.4 Real-time Timer Status Register Register Name: RTT_SR Address: 0x400E143C Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR.
SAM3N 14. Real Time Clock (RTC) 14.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator.
14.4 Product Dependencies 14.4.1 Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 14.4.2 Interrupt RTC interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the interrupt controller to be programmed first. 14.
14.5.4 Error Checking Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed.
Figure 14-2.
14.6 Real Time Clock (RTC) User Interface Table 14-1.
14.6.1 Name: RTC Control Register RTC_CR Address: 0x400E1460 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM This register can only be written if the WPEN bit is cleared in “RTC Write Protect Mode Register” on page 246. • UPDTIM: Update Request Time Register 0 = No effect.
14.6.2 Name: RTC Mode Register RTC_MR Address: 0x400E1464 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – HRMOD • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. All non-significant bits read zero.
14.6.3 Name: RTC Time Register RTC_TIMR Address: 0x400E1468 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units.
14.6.4 Name: RTC Calendar Register RTC_CALR Address: 0x400E146C Access: Read-write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19 - 20 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units.
14.6.5 Name: RTC Time Alarm Register RTC_TIMALR Address: 0x400E1470 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 11 MIN 6 5 SECEN 4 3 SEC This register can only be written if the WPEN bit is cleared in “RTC Write Protect Mode Register” on page 246. • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter.
14.6.6 Name: RTC Calendar Alarm Register RTC_CALALR Address: 0x400E1474 Access: Read-write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 20 19 15 14 13 12 11 10 9 8 – – – – – – – – MONTH 7 6 5 4 3 2 1 0 – – – – – – – – This register can only be written if the WPEN bit is cleared in “RTC Write Protect Mode Register” on page 246. • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter.
14.6.7 Name: RTC Status Register RTC_SR Address: 0x400E1478 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0 = Time and calendar registers cannot be updated. 1 = Time and calendar registers can be updated. • ALARM: Alarm Flag 0 = No alarm matching condition occurred.
14.6.8 Name: RTC Status Clear Command Register RTC_SCCR Address: 0x400E147C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0 = No effect.
14.6.9 Name: RTC Interrupt Enable Register RTC_IER Address: 0x400E1480 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0 = No effect. 1 = The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0 = No effect.
14.6.10 Name: RTC Interrupt Disable Register RTC_IDR Address: 0x400E1484 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0 = No effect. 1 = The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0 = No effect.
14.6.11 Name: RTC Interrupt Mask Register RTC_IMR Address: 0x400E1488 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. 1 = The acknowledge for update interrupt is enabled.
14.6.12 Name: RTC Valid Entry Register RTC_VER Address: 0x400E148C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0 = No invalid data has been detected in RTC_TIMR (Time Register). 1 = RTC_TIMR has contained invalid data since it was last programmed.
14.6.13 Name: RTC Write Protect Mode Register RTC_WPMR Address: 0x400E1544 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x525443 (“RTC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x525443 (“RTC” in ASCII).
SAM3N 15. Watchdog Timer (WDT) 15.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 15.
15.4 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
Figure 15-2.
15.5 Watchdog Timer (WDT) User Interface Table 15-1.
15.5.1 Name: Watchdog Timer Control Register WDT_CR Address: 0x400E1450 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
15.5.2 Name: Watchdog Timer Mode Register WDT_MR Address: 0x400E1454 Access: Read-write Once 31 30 23 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 11 22 26 25 24 18 17 16 10 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
15.5.3 Name: Watchdog Timer Status Register WDT_SR Address: 0x400E1458 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
SAM3N 11011B–ATARM–21-Feb-12
SAM3N 16. Supply Controller (SUPC) 16.1 Description The Supply Controller (SUPC) controls the supply voltage of the Core of the system and manages the Backup Low Power Mode. In this mode, the current consumption is reduced to a few microamps for Backup power retention. Exit from this mode is possible on multiple wake-up sources including events on WKUP pins, or a Clock alarm. The SUPC also generates the Slow Clock by selecting either the Low Power RC oscillator or the Low Power Crystal oscillator. 16.
16.3 Block Diagram Figure 16-1.
16.4 16.4.
16.4.2 Slow Clock Generator The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs). The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency.
16.4.4 Supply Monitor The Supply Controller embeds a supply monitor which is located in the VDDIO Power Supply and which monitors VDDIO power supply. The supply monitor can be used to prevent the processor from falling into an unpredictable state if the Main power supply drops below a certain level. The threshold of the supply monitor is programmable. It can be selected from 1.9V to 3.4V by steps of 100 mV.
Figure 16-2. Supply Monitor Status Bit and Associated Interrupt Continuous Sampling (SMSMPL = 1) Periodic Sampling Supply Monitor ON 3.
16.4.5 Power Supply Reset 16.4.5.1 Raising the Power Supply As soon as the voltage VDDIO rises, the RC oscillator is powered up and the zero-power power-on reset cell maintains its output low as long as VDDIO has not reached its target voltage. During this time, the Supply Controller is entirely reset. When the VDDIO voltage becomes valid and zero-power power-on reset signal is released, a counter is started for 5 slow clock cycles. This is the time it takes for the 32 kHz RC oscillator to stabilize.
16.4.6 Core Reset The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described previously in Section 16.4.5 ”Power Supply Reset”. The vddcore_nreset signal is normally asserted before shutting down the core power supply and released as soon as the core power supply is correctly regulated. There are two additional sources which can be programmed to activate vddcore_nreset: • a supply monitor detection • a brownout detection 16.4.6.
Figure 16-4. Wake Up Sources SMEN sm_out RTCEN rtc_alarm Core Supply Restart RTTEN rtt_alarm WKUPT0 WKUP0 16.4.7.1 WKUPDBC WKUPEN1 WKUPIS1 SLCK WKUPS Debouncer Falling/Rising Edge Detector WKUPT15 WKUP15 WKUPIS0 Falling/Rising Edge Detector WKUPT1 WKUP1 WKUPEN0 WKUPEN15 WKUPIS15 Falling/Rising Edge Detector Wake Up Inputs The wake up inputs, WKUP0 to WKUP15, can be programmed to perform a wake up of the core power supply.
16.4.7.2 Clock Alarms The RTC and the RTT alarms can generate a wake up of the core power supply. This can be enabled by writing respectively, the bits RTCEN and RTTEN to 1 in the Supply Controller Wake Up Mode Register (SUPC_WUMR). The Supply Controller does not provide any status as the information is available in the User Interface of either the Real Time Timer or the Real Time Clock. 16.4.7.3 264 Supply Monitor Detection The supply monitor can generate a wakeup of the core power supply.
16.5 Supply Controller (SUPC) User Interface The User Interface of the Supply Controller is part of the System Controller User Interface. 16.5.1 System Controller (SYSC) User Interface Table 16-1. System Controller Registers Offset System Controller Peripheral Name 0x00-0x0c Reset Controller RSTC 0x10-0x2C Supply Controller SUPC 0x30-0x3C Real Time Timer RTT 0x50-0x5C Watchdog WDT 0x60-0x7C Real Time Clock RTC 0x90-0xDC General Purpose Backup Register GPBR 16.5.
16.5.3 Name: Supply Controller Control Register SUPC_CR Address: 0x400E1410 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 XTALSEL 2 VROFF 1 – 0 – • VROFF: Voltage Regulator Off 0 (NO_EFFECT) = no effect. 1 (STOP_VREG) = if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. • XTALSEL: Crystal Oscillator Select 0 (NO_EFFECT) = no effect.
16.5.4 Name: Supply Controller Supply Monitor Mode Register SUPC_SMMR Address: 0x400E1414 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 SMIEN 12 SMRSTEN 11 – 10 9 SMSMPL 8 7 – 6 – 5 – 4 – 3 2 1 0 SMTH • SMTH: Supply Monitor Threshold 267 Value Name Description 0x0 1_9V 1.9 V 0x1 2_0V 2.0 V 0x2 2_1V 2.1 V 0x3 2_2V 2.2 V 0x4 2_3V 2.3 V 0x5 2_4V 2.4 V 0x6 2_5V 2.5 V 0x7 2_6V 2.
• SMSMPL: Supply Monitor Sampling Period Value Name Description 0x0 SMD Supply Monitor disabled 0x1 CSM Continuous Supply Monitor 0x2 32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods 0x3 256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods 0x4 2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods 0x5-0x7 Reserved Reserved • SMRSTEN: Supply Monitor Reset Enable 0 (NOT_ENABLE) = the core reset signal “vddcore_nreset” is not affected w
16.5.5 Name: Supply Controller Mode Register SUPC_MR Address: 0x400E1418 Access: Read-write 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 OSCBYPASS 19 – 18 – 17 – 16 – 15 – 14 ONREG 13 BODDIS 12 BODRSTEN 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • BODRSTEN: Brownout Detector Reset Enable 0 (NOT_ENABLE) = the core reset signal “vddcore_nreset” is not affected when a brownout detection occurs.
16.5.6 Name: Supply Controller Wake Up Mode Register SUPC_WUMR Address: 0x400E141C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 13 WKUPDBC 12 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 RTCEN 2 RTTEN 1 SMEN 0 – • SMEN: Supply Monitor Wake Up Enable 0 (NOT_ENABLE) = the supply monitor detection has no wake up effect. 1 (ENABLE) = the supply monitor detection forces the wake up of the core power supply.
16.5.
16.5.
SAM3N 17. General Purpose Backup Registers (GPBR) 17.1 Description The System Controller embeds Eight general-purpose backup registers. 17.2 Embedded Characteristics Eight 32-bit General Purpose Backup Registers 17.3 General Purpose Backup Registers (GPBR) User Interface Table 17-1. Register Mapping Offset 0x0 ... 0x1C Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 7 SYS_GPBR7 Access Reset Read-write – ... ...
SAM3N 17.3.0.1 Name: General Purpose Backup Register x SYS_GPBRx Addresses: 0x400E1490 [0] ..
SAM3N 18. Enhanced Embedded Flash Controller (EEFC) 18.1 Description The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
Figure 18-1.
SAM3N 18.3.2 Read Operations An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in Thumb2 mode by means of the 128- or 64- bit wide memory interface. The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it.
Figure 18-3.
SAM3N 18.3.3 Flash Commands The Enhanced Embedded Flash Controller (EEFC) offers a set of commands such as programming the memory Flash, locking and unlocking lock regions, consecutive programming and locking and full Flash erasing, etc. Commands and read operations can be performed in parallel only on different memory planes. Code can be fetched from one memory plane while a write or an erase operation is performed on another. Table 18-2.
Figure 18-5. Command State Chart Read Status: MC_FSR No Check if FRDY flag Set Yes Write FCMD and PAGENB in Flash Command Register Read Status: MC_FSR No Check if FRDY flag Set Yes Check if FLOCKE flag Set Yes Locking region violation No Check if FCMDE flag Set Yes Bad keyword violation No Command Successfull 18.3.3.1 Getting Embedded Flash Descriptor This command allows the system to learn about the Flash organization. The system can take full advantage of this information.
SAM3N ations to the EEFC_FRR register are done after the last word of the descriptor has been returned, then the EEFC_FRR register value is 0 until the next valid command. Table 18-3. Flash Descriptor Definition Symbol Word Index Description FL_ID 0 Flash Interface Description FL_SIZE 1 Flash size in bytes FL_PAGE_SIZE 2 Page size in bytes FL_NB_PLANE 3 Number of planes. FL_PLANE[0] 4 Number of bytes in the first plane. 4 + FL_NB_PLANE - 1 Number of bytes in the last plane.
Two errors can be detected in the EEFC_FSR register after a programming sequence: • a Command Error: a bad keyword has been written in the EEFC_FCR register. • a Lock Error: the page to be programmed belongs to a locked region. A command must be previously run to unlock the corresponding region. By using the WP command, a page can be programmed in several steps if it has been erased before (see Figure 18-6). Figure 18-6.
SAM3N The lock sequence is: • The Set Lock command (SLB) and a page number to be protected are written in the Flash Command Register. • When the locking completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated. • If the lock bit number is greater than the total number of lock bits, then the command has no effect.
• When the GPVNM bit is set, the bit FRDY in the Flash Programming Status Register (EEFC_FSR) rises. If an interrupt was enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated. • If the GPNVM bit number is greater than the total number of GPNVM bits, then the command has no effect. The result of the SGPB command can be checked by running a GGPB (Get GPNVM Bit) command.
SAM3N The 4/8/12 MHz Fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB Bit command. The table below shows the bit implementation for each frequency: RC Calibration Frequency EEFC_FRR Bits 8 MHz output [28 - 22] 12 MHz output [38 - 32] The RC calibration for 4 MHz is set to 1,000,000. 18.3.3.
18.4 Enhanced Embedded Flash Controller (EEFC) User Interface The User Interface of the Enhanced Embedded Flash Controller (EEFC) is integrated within the System Controller with base address 0x400E0800. Table 18-4.
SAM3N 18.4.1 Name: EEFC Flash Mode Register EEFC_FMR Address: 0x400E0A00 Access: Read-write Offset: 0x00 31 30 29 28 27 26 25 24 – – – – – – – FAM 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – 7 6 5 4 3 2 1 0 – – – – – FRDY – FWS • FRDY: Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready (to accept a new command) generates an interrupt.
18.4.2 Name: EEFC Flash Command Register EEFC_FCR Address: 0x400E0A04 Access: Write-only Offset: 0x04 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FKEY 23 22 21 20 FARG 15 14 13 12 FARG 7 6 5 4 FCMD • FCMD: Flash Command This field defines the flash commands. Refer to “Flash Commands” on page 279. • FARG: Flash Command Argument Erase command For erase all command, this field is meaningless. Programming command FARG defines the page number to be programmed.
SAM3N 18.4.3 Name: EEFC Flash Status Register EEFC_FSR Address: 0x400E0A08 Access: Read-only Offset: 0x08 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – FLOCKE FCMDE FRDY • FRDY: Flash Ready Status 0: The Enhanced Embedded Flash Controller (EEFC) is busy. 1: The Enhanced Embedded Flash Controller (EEFC) is ready to start a new command.
18.4.4 Name: EEFC Flash Result Register EEFC_FRR Address: 0x400E0A0C Access: Read-only Offset: 0x0C 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FVALUE 23 22 21 20 FVALUE 15 14 13 12 FVALUE 7 6 5 4 FVALUE • FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, then the next resulting value is accessible at the next register read.
SAM3N 19. Fast Flash Programming Interface (FFPI) 19.1 Description The Fast Flash Programming Interface provides parallel high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities.
Table 19-1.
SAM3N 19.2.2 Signal Names Depending on the MODE settings, DATA is latched in different internal registers. Table 19-2. Mode Coding MODE[3:0] Symbol Data 0000 CMDE Command Register 0001 ADDR0 Address Register LSBs 0010 ADDR1 0011 ADDR2 0100 ADDR3 Address Register MSBs 0101 DATA Data Register Default IDLE No register When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] or DATA[7:0] signals) is stored in the command register.
19.2.3 Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: • Apply GND, VDDIO, VDDCORE and VDDPLL. • Apply XIN clock within TPOR_RESET if an external clock is available. • Wait for TPOR_RESET • Start a read or write handshaking. 19.2.4 19.2.4.1 Programmer Handshaking An handshake is defined for read and write operations. When the device is ready to start a new operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal.
SAM3N Table 19-4. Write Handshake Step Programmer Action Device Action Data I/O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latches MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input 4 Releases MODE and DATA signals Executes command and polls NCMD high Input 5 Sets NCMD signal Executes command and polls NCMD high Input 6 Waits for RDY high Sets RDY Input 19.2.4.
Table 19-5. Read Handshake Step Programmer Action Device Action DATA I/O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latch MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input 4 Sets DATA signal in tristate Waits for NOE Low Input 5 Clears NOE signal 6 Waits for NVALID low 7 Tristate Sets DATA bus in output mode and outputs the flash contents.
SAM3N 19.2.5 Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 19-3 on page 293. Each command is driven by the programmer through the parallel interface running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command after a write automatically flushes the load buffer in the Flash.
Table 19-7. 19.2.5.2 Read Command (Continued) Step Handshake Sequence MODE[3:0] DATA[7:0] n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking ADDR2 Memory Address n+3 Write handshaking ADDR3 Memory Address n+4 Read handshaking DATA *Memory Address++ n+5 Read handshaking DATA *Memory Address++ ... ... ... ... Flash Write Command This command is used to write the Flash contents. The Flash memory plane is organized into several pages.
SAM3N Table 19-9. Write Command (Continued) Step Handshake Sequence MODE[3:0] DATA[7:0] 5 Write handshaking ADDR3 Memory Address 6 Write handshaking DATA *Memory Address++ 7 Write handshaking DATA *Memory Address++ ... ... ... ...
In the same way, the Clear Lock command (CLB) is used to clear lock bits. Table 19-11. Set and Clear Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0] 1 Write handshaking CMDE SLB or CLB 2 Write handshaking DATA Bit Mask Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is set.. Table 19-12. Get Lock Bit Command 19.2.5.
SAM3N 19.2.5.6 Flash Security Bit Command A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit once the contents of the Flash have been erased. Table 19-15.
Table 19-17. Write Command 19.2.5.8 Step Handshake Sequence MODE[3:0] DATA[7:0] 1 Write handshaking CMDE WRAM 2 Write handshaking ADDR0 Memory Address LSB 3 Write handshaking ADDR1 Memory Address 4 Write handshaking ADDR2 Memory Address 5 Write handshaking ADDR3 Memory Address 6 Write handshaking DATA *Memory Address++ 7 Write handshaking DATA *Memory Address++ ... ... ... ...
SAM3N 20. SAM3N Boot Program 20.1 Description The SAM-BA® Boot Program integrates an array of programs permitting download and/or upload into the different memories of the product. 20.2 Hardware and Software Constraints • SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available size can be used for user's code. • UART0 requirements: None Table 20-1. 20.
20.5 SAM-BA Monitor The SAM-BA boot principle: Once the communication interface is identified, to run in an infinite loop waiting for different commands as shown in Table 20-2. Table 20-2.
SAM3N – Output: ‘>’ • Get Version (V): Return the SAM-BA boot version – Output: ‘>’ 20.5.1 UART0 Serial Port Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product.
SAM3N 20.5.3 In Application Programming (IAP) Feature The IAP feature is a function located in ROM that can be called by any software application. When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready (looping while the FRDY bit is not set in the MC_FSR register). Since this function is executed from ROM, this allows Flash programming (such as sector write) to be done by code running in Flash.
SAM3N 21. Bus Matrix (MATRIX) 21.1 Description The Bus Matrix implements a multi-layer AHB that enables parallel access paths between multiple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 3 AHB Masters to 4 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
21.2.3 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not wired and shown as “-” in the following table. Table 21-2. SAM3N Master to Slave Access Masters Slaves 21.
SAM3N FIXED_DEFMSTR field allows to choose a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user interface description. 21.5 Arbitration The Bus Matrix provides an arbitration mechanism that allows to reduce latency when conflict cases occur, basically when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, allowing to arbitrate each slave differently.
This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG). 21.5.1.2 21.5.2 Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a very slow slave (e.g. an external low speed memory). At the beginning of the burst access, a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle.
SAM3N more master’s requests with the same priority are active at the same time, the master with the highest number is serviced first. For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS and MATRIX_PRBS). 21.6 System I/O Configuration The System I/O Configuration register (CCFG_SYSIO) allows to configure some I/O lines in System I/O mode (such as JTAG, ERASE, etc...) or as general purpose I/O lines.
SAM3N 21.8 Bus Matrix (MATRIX) User Interface Table 21-3.
SAM3N 21.8.1 Name: Bus Matrix Master Configuration Registers MATRIX_MCFG0..MATRIX_MCFG2 Address: 0x400E0200 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – ULBT • ULBT: Undefined Length Burst Type 0: Infinite Length Burst No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
SAM3N 21.8.2 Name: Bus Matrix Slave Configuration Registers MATRIX_SCFG0..
SAM3N 21.8.3 Name: Bus Matrix Priority Registers For Slaves MATRIX_PRAS0..MATRIX_PRAS3 Addresses: 0x400E0280 [0], 0x400E0288 [1], 0x400E0290 [2], 0x400E0298 [3] Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 – – – – 7 6 3 2 – – – – M3PR 5 4 M1PR 8 M2PR 1 0 M0PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave.
21.8.4 System I/O Configuration Register Name: CCFG_SYSIO Address: 0x400E0314 Access Read-write Reset: 0x0000_0000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – SYSIO12 – – – – 7 6 5 4 3 2 1 0 SYSIO7 SYSIO6 SYSIO5 SYSIO4 – – – – • SYSIO4: PB4 or TDI Assignment 0 = TDI function selected. 1 = PB4 function selected.
SAM3N 21.8.5 Name: Write Protect Mode Register MATRIX_WPMR Address: 0x400E03E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN For more details on MATRIX_WPMR, refer to Section 21.7 “Write Protect Registers” on page 311. • WPEN: Write Protect ENable 0 = Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
21.8.6 Name: Write Protect Status Register MATRIX_WPSR Address: 0x400E03E8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS For more details on MATRIX_WPSR, refer to Section 21.7 “Write Protect Registers” on page 311. • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of MATRIX_WPMR.
SAM3N 22. Peripheral DMA Controller (PDC) 22.1 Description The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by the AHB to ABP bridge. The user interface of each PDC channel is integrated into the user interface of the peripheral it serves.
22.3 Block Diagram Figure 22-1.
SAM3N 22.4 22.4.1 Functional Description Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR).
The following list gives an overview of how status register flags behave depending on the counters’ values: • ENDRX flag is set when the PERIPH_RCR register reaches zero. • RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero. • ENDTX flag is set when the PERIPH_TCR register reaches zero. • TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero. These status flags are described in the Peripheral Status Register. 22.4.
SAM3N 22.4.5.4 Transmit Buffer Empty This flag is set when PERIPH_TCR register reaches zero with PERIPH_TNCR also set to zero and the last data has been written into peripheral THR. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
22.5 Peripheral DMA Controller (PDC) User Interface Table 22-2.
SAM3N 22.5.1 Name: Receive Pointer Register PERIPH_RPR Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
22.5.2 Name: Receive Counter Register PERIPH_RCR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXCTR 7 6 5 4 RXCTR • RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
SAM3N 22.5.3 Name: Transmit Pointer Register PERIPH_TPR Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
SAM3N 22.5.4 Name: Transmit Counter Register PERIPH_TCR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXCTR 7 6 5 4 TXCTR • TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
SAM3N 22.5.5 Name: Receive Next Pointer Register PERIPH_RNPR Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR • RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. 22.5.
SAM3N 22.5.7 Name: Transmit Next Pointer Register PERIPH_TNPR Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR • TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. 22.5.
SAM3N 22.5.9 Name: Transfer Control Register PERIPH_PTCR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 TXTDIS 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXTDIS 0 RXTEN • RXTEN: Receiver Transfer Enable 0 = No effect. 1 = Enables PDC receiver channel requests if RXTDIS is not set.
22.5.10 Name: Transfer Status Register PERIPH_PTSR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RXTEN • RXTEN: Receiver Transfer Enable 0 = PDC Receiver channel requests are disabled. 1 = PDC Receiver channel requests are enabled. • TXTEN: Transmitter Transfer Enable 0 = PDC Transmitter channel requests are disabled.
SAM3N 23. Clock Generator 23.1 Description The Clock Generator User Interface is embedded within the Power Management Controller and is described in Section 24.15 ”Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are named CKGR_. 23.
23.3 Block Diagram Figure 23-1.
SAM3N 23.4 Slow Clock The Supply Controller embeds a slow clock generator that is supplied with the VDDIO powersupply. As soon as VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs). The Slow Clock is generated either by the Slow Clock Crystal Oscillator or by the Slow Clock RC Oscillator.
the XIN32 pin are given in the product electrical characteristics section. In order to set the bypass mode, the OSCBYPASS bit of the Supply Controller Mode Register (SUPC_MR) needs to be set at 1. The user can set the Slow Clock Crystal Oscillator in bypass mode instead of connecting a crystal. In this case, the user has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin under these conditions are given in the product electrical characteristics section.
SAM3N 23.5.1 4/8/12 MHz Fast RC Oscillator After reset, the 4/8/12 MHz Fast RC Oscillator is enabled with the 4 MHz frequency selected and it is selected as the source of MAINCK. MAINCK is the default clock selected to start up the system. The Fast RC Oscillator 8 and 12 MHz frequencies are calibrated in production. Note that is not the case for the 4 MHz frequency. Please refer to the “DC Characteristics” section of the product datasheet.
23.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator After reset, the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is disabled and it is not selected as the source of MAINCK. The user can select the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to be the source of MAINCK, as it provides a more accurate frequency. The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCXTEN bit in the Main Oscillator Register (CKGR_MOR).
SAM3N Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock Frequency Register (CKGR_MCFR) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the 4/8/12 MHz Fast RC oscillator or 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator can be determined.
23.6 Divider and PLL Block The device features a Divider/PLL Block that permits a wide range of frequencies to be selected on either the master clock, the processor clock or the programmable clock outputs. Figure 23-4 shows the block diagram of the divider and PLL block. Figure 23-4. Divider and PLL Block Diagram DIV MAINCK Divider MUL OUT PLL PLLCK PLLCOUNT SLCK 23.6.1 PLL Counter LOCK Divider and Phase Lock Loop Programming The divider can be set between 1 and 255 in steps of 1.
SAM3N 24. Power Management Controller (PMC) 24.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Cortex-M3 Processor. The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized.
24.3 Block Diagram Figure 24-1. General Clock Block Diagram Clock Generator Processor Clock Controller EXTALSEL (Supply Controller) Processor clock HCLK int Sleep Mode Embedded 32 kHz RC Oscillator 0 Divider /8 Slow Clock SLCK XIN32 XOUT32 32768 Hz Crystal Oscillator XOUT Free runnning clock FCLK Master clock MCK Prescaler /1,/2,/3,/4,...
SAM3N Figure 24-2. Master Clock Controller PMC_MCKR PMC_MCKR CSS PRES SLCK MAINCK Master Clock Prescaler MCK PLLCK To the Processor Clock Controller (PCK) 24.5 Processor Clock Controller The PMC features a Processor Clock Controller (HCLK) that implements the Processor Sleep Mode. The Processor Clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Startup Mode Register (PMC_FSMR).
24.8 Free Running Processor Clock The Free running processor clock (FCLK) used for sampling interrupts and clocking debug blocks ensures that interrupts can be sampled, and sleep events can be traced, while the processor is sleeping. It is connected to Master Clock (MCK). 24.9 Programmable Clock Output Controller The PMC controls 3 signals to be output on external pins, PCKx. Each signal can be independently programmed via the PMC_PCKx registers.
SAM3N 24.10 Fast Startup The SAM3N device allows the processor to restart in less than10 µs while the device is in Wait mode. The system enters Wait mode either by writing the WAITMODE bit at 1 in the PMC Clock Generator Main Oscillator Register (CKGR_MOR), or by executing the WaitForEvent (WFE) instruction of the processor while the LPM bit is at 1 in the PMC Fast Startup Mode Register (PMC_FSMR).
24.11 Clock Failure Detector The clock failure detector allows to monitor the 3 to 20 MHz Crystal or Ceramic Resonatorbased oscillator and to detect an eventual defect of this oscillator (for example if the crystal is unconnected). The clock failure detector can be enabled or disabled by means of the CFDEN bit in the PMC Clock Generator Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled.
SAM3N 24.12 Programming Sequence 1. Enabling the Main Oscillator: The main oscillator is enabled by setting the MOSCXTEN field in the CKGR_MOR register. The user can define a start-up time. This can be achieved by writing a value in the MOSCXTST field in the CKGR_MOR register. Once this register has been correctly configured, the user must wait for MOSCXTS field in the PMC_SR register to be set.
• If a new value for CSS field corresponds to PLL Clock, – Program the PRES field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. – Program the CSS field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. • If a new value for CSS field corresponds to Main Clock or Slow Clock, – Program the CSS field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. – Program the PRES field in the PMC_MCKR register.
SAM3N Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write operation.
24.13 Clock Switching Details 24.13.1 Master Clock Switching Timings Table 24-1 gives the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 24-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLL Clock – 4 x SLCK + 2.
SAM3N Figure 24-5. Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR Figure 24-6.
Figure 24-7.
SAM3N 24.14 Write Protection Registers To prevent any single software error that may corrupt PMC behavior, certain address spaces can be write protected by setting the WPEN bit in the “PMC Write Protect Mode Register” (PMC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the PMC Write Protect Status Register (PMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
24.15 Power Management Controller (PMC) User Interface Table 24-2.
SAM3N 24.15.1 Name: PMC System Clock Enable Register PMC_SCER Address: 0x400E0400 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 – – – – – – – – This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 374. • PCKx: Programmable Clock x Output Enable 0 = No effect.
24.15.3 Name: PMC System Clock Status Register PMC_SCSR Address: 0x400E0408 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 – – – – – – – – • PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled. 1 = The corresponding Programmable Clock output is enabled.
SAM3N 24.15.
24.15.
SAM3N 24.15.
24.15.7 Name: PMC Clock Generator Main Oscillator Register CKGR_MOR Address: 0x400E0420 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 CFDEN 24 MOSCSEL 19 18 17 16 11 10 9 8 3 MOSCRCEN 2 WAITMODE 1 MOSCXTBY 0 MOSCXTEN KEY 15 14 13 12 MOSCXTST 7 – 6 5 MOSCRCF 4 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 374. • KEY: Password Should be written at value 0x37.
SAM3N • MOSCRCF: Main On-Chip RC Oscillator Frequency Selection Value Name Description 0x0 4MHZ The Fast RC Oscillator Frequency is at 4 MHz (default) 0x1 8MHZ The Fast RC Oscillator Frequency is at 8 MHz 0x2 12MHZ The Fast RC Oscillator Frequency is at 12 MHz • MOSCXTST: Main Crystal Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Crystal Oscillator start-up time. • MOSCSEL: Main Oscillator Selection 0 = The Main On-Chip RC Oscillator is selected.
24.15.8 Name: PMC Clock Generator Main Clock Frequency Register CKGR_MCFR Address: 0x400E0424 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 MAINFRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 374. • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods.
SAM3N 24.15.9 Name: PMC Clock Generator PLL Register CKGR_PLLR Address: 0x400E0428 Access: Read-write 31 – 30 – 29 1 28 – 23 22 21 20 27 – 26 25 MUL 24 19 18 17 16 10 9 8 2 1 0 MUL 15 – 14 – 13 7 6 5 12 11 PLLCOUNT 4 3 DIV Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLR register.
24.15.10 PMC Master Clock Register Name: PMC_MCKR Address: 0x400E0430 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – PLLDIV2 – – – – 7 6 5 4 3 2 1 – – – PRES 0 CSS This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 374.
SAM3N 24.15.11 PMC Programmable Clock Register Name: PMC_PCKx Address: 0x400E0440 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – PRES – CSS This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 374.
24.15.
SAM3N 24.15.
24.15.14 PMC Status Register Name: PMC_SR Address: 0x400E0468 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – FOS CFDS CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 – – – – – PCKRDY2 PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 OSCSELS – – – MCKRDY – LOCK MOSCXTS • MOSCXTS: Main XTAL Oscillator Status 0 = Main XTAL oscillator is not stabilized. 1 = Main XTAL oscillator is stabilized.
SAM3N • CFDS: Clock Failure Detector Status 0 = A clock failure of the main on-chip RC oscillator clock is not detected. 1 = A clock failure of the main on-chip RC oscillator clock is detected. • FOS: Clock Failure Detector Fault Output Status 0 = The fault output of the clock failure detector is inactive. 1 = The fault output of the clock failure detector is active.
24.15.
SAM3N 24.15.16 PMC Fast Startup Mode Register Name: PMC_FSMR Address: 0x400E0470 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 LPM 19 – 18 – 17 RTCAL 16 RTTAL 15 FSTT15 14 FSTT14 13 FSTT13 12 FSTT12 11 FSTT11 10 FSTT10 9 FSTT9 8 FSTT8 7 FSTT7 6 FSTT6 5 FSTT5 4 FSTT4 3 FSTT3 2 FSTT2 1 FSTT1 0 FSTT0 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 374.
24.15.17 PMC Fast Startup Polarity Register Name: PMC_FSPR Address: 0x400E0474 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 FSTP15 14 FSTP14 13 FSTP13 12 FSTP12 11 FSTP11 10 FSTP10 9 FSTP9 8 FSTP8 7 FSTP7 6 FSTP6 5 FSTP5 4 FSTP4 3 FSTP3 2 FSTP2 1 FSTP1 0 FSTP0 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 374.
SAM3N 24.15.18 PMC Fault Output Clear Register Name: PMC_FOCR Address: 0x400E0478 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FOCLR • FOCLR: Fault Output Clear Clears the clock failure detector fault output.
24.15.19 PMC Write Protect Mode Register Name: PMC_WPMR Address: 0x400E04E4 Access: Read-write Reset: See Table 24-2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
SAM3N 24.15.20 PMC Write Protect Status Register Name: PMC_WPSR Address: 0x400E04E8 Access: Read-only Reset: See Table 24-2 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the PMC_WPSR register.
24.15.21 PMC Oscillator Calibration Register Name: PMC_OCR Address: 0x400E0510 Access: Read-Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 SEL12 22 21 20 19 CAL12 18 17 16 15 SEL8 14 13 12 11 CAL8 10 9 8 7 SEL4 6 5 4 3 CAL4 2 1 0 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 374. • CAL4: RC Oscillator Calibration bits for 4 MHz Calibration bits applied to the RC Oscillator when SEL4 is set.
SAM3N 25. Chip Identifier (CHIPID) 25.1 Description Chip Identifier registers permit recognition of the device and its revision. These registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Two chip identifier registers are embedded: CHIPID_CIDR (Chip ID Register) and CHIPID_EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
25.2 Chip Identifier (CHIPID) User Interface Table 25-2.
SAM3N 25.2.1 Name: Chip ID Register CHIPID_CIDR Address: 0x400E0740 Access: Read-only 31 30 29 EXT 28 27 26 NVPTYP 23 22 21 20 19 18 ARCH 15 14 13 6 24 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 25 ARCH NVPSIZ 5 4 EPROC 3 2 VERSION • VERSION: Version of the Device Current version of the device.
Value Name 13 14 Description Reserved 2048K 15 2048K bytes Reserved • NVPSIZ2 Second Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8K bytes 2 16K 16K bytes 3 32K 32K bytes 4 5 Reserved 64K 6 7 64K bytes Reserved 128K 8 128K bytes Reserved 9 256K 256K bytes 10 512K 512K bytes 11 12 Reserved 1024K 13 14 1024K bytes Reserved 2048K 15 2048K bytes Reserved • SRAMSIZ: Internal SRAM Size Value 380 Name Description 0 48K 48K bytes 1 1K 1K
SAM3N Value Name Description 13 256K 256K bytes 14 96K 96K bytes 15 512K 512K bytes • ARCH: Architecture Identifier Value Name Description 0x19 AT91SAM9xx AT91SAM9xx Series 0x29 AT91SAM9XExx AT91SAM9XExx Series 0x34 AT91x34 AT91x34 Series 0x37 CAP7 CAP7 Series 0x39 CAP9 CAP9 Series 0x3B CAP11 CAP11 Series 0x40 AT91x40 AT91x40 Series 0x42 AT91x42 AT91x42 Series 0x55 AT91x55 AT91x55 Series 0x60 AT91SAM7Axx AT91SAM7Axx Series 0x61 AT91SAM7AQxx AT91SAM7AQxx Series
Value Name Description 0x98 ATSAM3SDxA ATSAM3SDxA Series (48-pin version) 0x99 ATSAM3SDxB ATSAM3SDxB Series (64-pin version) 0x9A ATSAM3SDxC ATSAM3SDxC Series (100-pin version) 0xA5 ATSAM5A ATSAM5A 0xF0 AT75Cxx AT75Cxx Series • NVPTYP: Nonvolatile Program Memory Type Value Name Description 0 ROM ROM 1 ROMLESS ROMless or on-chip Flash 4 SRAM SRAM emulating ROM 2 FLASH Embedded Flash Memory 3 ROM_FLASH ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size •
SAM3N 25.2.2 Name: Chip ID Extension Register CHIPID_EXID Address: 0x400E0744 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in CHIPID_CIDR is 0.
SAM3N 11011B–ATARM–21-Feb-12
SAM3N 26. Parallel Input/Output (PIO) Controller 26.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
26.3 Block Diagram Figure 26-1. Block Diagram PIO Controller Interrupt Controller PIO Interrupt PIO Clock PMC Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Up to 32 peripheral IOs Embedded Peripheral PIN 31 APB Figure 26-2.
SAM3N 26.4 Product Dependencies 26.4.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e.
26.5 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 26-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 26-3.
SAM3N 26.5.1 Pull-up and Pull-down Resistor Control Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register).
• the corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 1 in PIO_ABCDSR2 means peripheral D is selected. Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.
SAM3N The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. 26.5.
• If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 Period of the Programmable Divided Slow Clock. For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV field of the PIO_SCDR (Slow Clock Divider Register) Tdiv_slclk = ((DIV+1)*2).
SAM3N Figure 26-6. Input Debouncing Filter Timing PIO_IFCSR = 1 Divided Slow Clock Pin Level up to 2 cycles Tmck up to 2 cycles Tmck PIO_PDSR if PIO_IFSR = 0 1 cycle Tdiv_slclk up to 1.5 cycles Tdiv_slclk PIO_PDSR if PIO_IFSR = 1 up to 1.5 cycles Tdiv_slclk up to 2 cycles Tmck 26.5.10 1 cycle Tdiv_slclk up to 2 cycles Tmck Input Edge/Level Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line.
Level is selected in the PIO_ELSR). The current status of this selection is accessible through the PIO_FRLHSR (Fall/Rise - Low/High Status Register). When an input Edge or Level is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the .
SAM3N 26.5.10.2 Interrupt Mode Configuration All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER. Then the Additional Interrupt Mode is enabled for line 0 to 7 by writing 32’h0000_00FF in PIO_AIMER. 26.5.10.3 Edge or Level Detection Configuration Lines 3, 4 and 5 are configured in Level detection by writing 32’h0000_0038 in PIO_LSR. The other lines are configured in Edge detection by default, if they have not been previously configured.
26.5.13 Write Protection Registers To prevent any single software error that may corrupt PIO behavior, certain address spaces can be write-protected by setting the WPEN bit in the “PIO Write Protect Mode Register” (PIO_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Protect Status Register (PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
SAM3N 26.6 I/O Lines Programming Example The programing example as shown in Table 26-1 below is used to obtain the following configuration.
26.7 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 26-2.
SAM3N Table 26-2.
Table 26-2. Register Mapping (Continued) Offset Register Name 0x01040x010C Reserved 0x0110 0x01140x011C Notes: Access Reset – – – Reserved – – – Reserved – – – 1. Reset value of PIO_PSR depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines.
SAM3N 26.7.1 Name: PIO Enable Register PIO_PER Addresses: 0x400E0E00 (PIOA), 0x400E1000 (PIOB), 0x400E1200 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
26.7.3 Name: PIO Status Register PIO_PSR Addresses: 0x400E0E08 (PIOA), 0x400E1008 (PIOB), 0x400E1208 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active).
SAM3N 26.7.
26.7.
SAM3N 26.7.9 Name: PIO Input Filter Status Register PIO_IFSR Addresses: 0x400E0E28 (PIOA), 0x400E1028 (PIOB), 0x400E1228 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line.
26.7.11 Name: PIO Clear Output Data Register PIO_CODR Addresses: 0x400E0E34 (PIOA), 0x400E1034 (PIOB), 0x400E1234 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Clear Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line. 26.7.
SAM3N 26.7.13 Name: PIO Pin Data Status Register PIO_PDSR Addresses: 0x400E0E3C (PIOA), 0x400E103C (PIOB), 0x400E123C (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1.
26.7.15 Name: PIO Interrupt Disable Register PIO_IDR Addresses: 0x400E0E44 (PIOA), 0x400E1044 (PIOB), 0x400E1244 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0 = No effect.
SAM3N 26.7.
26.7.
SAM3N 26.7.
26.7.23 Name: PIO Pull Up Status Register PIO_PUSR Addresses: 0x400E0E68 (PIOA), 0x400E1068 (PIOB), 0x400E1268 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line.
SAM3N 26.7.24 Name: PIO Peripheral ABCD Select Register 1 PIO_ABCDSR1 Access: Read-write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” . • P0-P31: Peripheral Select.
26.7.25 Name: Access: PIO Peripheral ABCD Select Register 2 PIO_ABCDSR2 Read-write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” . • P0-P31: Peripheral Select.
SAM3N 26.7.26 Name: PIO Input Filter Slow Clock Disable Register PIO_IFSCDR Addresses: 0x400E0E80 (PIOA), 0x400E1080 (PIOB), 0x400E1280 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Clock Glitch Filtering Select. 0 = No Effect.
26.7.
SAM3N 26.7.
26.7.
SAM3N 26.7.
26.7.35 Name: PIO Output Write Status Register PIO_OWSR Addresses: 0x400E0EA8 (PIOA), 0x400E10A8 (PIOB), 0x400E12A8 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line.
SAM3N 26.7.37 Name: PIO Additional Interrupt Modes Disable Register PIO_AIMDR Addresses: 0x400E0EB4 (PIOA), 0x400E10B4 (PIOB), 0x400E12B4 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Additional Interrupt Modes Disable. 0 = No effect.
26.7.39 Name: PIO Edge Select Register PIO_ESR Addresses: 0x400E0EC0 (PIOA), 0x400E10C0 (PIOB), 0x400E12C0 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge Interrupt Selection. 0 = No effect. 1 = The interrupt source is an Edge detection event.
SAM3N 26.7.41 Name: PIO Edge/Level Status Register PIO_ELSR Addresses: 0x400E0EC8 (PIOA), 0x400E10C8 (PIOB), 0x400E12C8 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge/Level Interrupt source selection.
26.7.43 Name: PIO Rising Edge/High Level Select Register PIO_REHLSR Addresses: 0x400E0ED4 (PIOA), 0x400E10D4 (PIOB), 0x400E12D4 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Rising Edge /High Level Interrupt Selection. 0 = No effect.
SAM3N 26.7.45 Name: PIO Lock Status Register PIO_LOCKSR Addresses: 0x400E0EE0 (PIOA), 0x400E10E0 (PIOB), 0x400E12E0 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Lock Status. 0 = The I/O line is not locked. 1 = The I/O line is locked.
26.7.46 Name: PIO Write Protect Mode Register PIO_WPMR Addresses: 0x400E0EE4 (PIOA), 0x400E10E4 (PIOB), 0x400E12E4 (PIOC) Access: Read-write Reset: See Table 26-2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN For more information on Write Protection Registers, refer to Section 26.7 ”Parallel Input/Output Controller (PIO) User Interface”.
SAM3N • WPKEY: Write Protect KEY Should be written at value 0x50494F (“PIO” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 26.7.
26.7.
SAM3N 27. Serial Peripheral Interface (SPI) 27.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
27.3 Block Diagram Figure 27-1. Block Diagram PDC APB SPCK MISO PMC MOSI MCK SPI Interface PIO NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 27.4 Application Block Diagram Figure 27-2.
SAM3N 27.5 Signal Description Table 27-1. Signal Description Type Pin Name Pin Description Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input 27.6 27.6.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
27.6.3 Interrupt The SPI interface has an interrupt line connected to the Nested Vector Interrupt Controller (NVIC).Handling the SPI interrupt requires programming the NVIC before configuring the SPI. Table 27-3. 27.7 Peripheral IDs Instance ID SPI 21 Functional Description 27.7.1 Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register.
SAM3N Figure 27-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 27-4.
27.7.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
SAM3N 27.7.3.1 Master Mode Block Diagram Figure 27-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TD TDRE SPI_CSR0..
27.7.3.2 Master Mode Flow Diagram Figure 27-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
SAM3N Figure 27-7 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved. Figure 27-7.
Figure 27-8. PDC Status Register Flags Behavior 1 3 2 SPCK NPCS0 MOSI (from master) MISO (from slave) MSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB ENDTX ENDRX TXBUFE RXBUFF TXEMPTY 27.7.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255.
SAM3N Figure 27-9. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS 27.7.3.5 DLYBS DLYBCT DLYBCT Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. • Fixed Peripheral Select: SPI exchanges data with only one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register).
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to.
SAM3N If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must be disabled. This is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0. Figure 27-10. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI SPCK MISO MOSI SPCK MISO MOSI SPCK MISO MOSI Slave 0 Slave 1 Slave 14 NSS NSS SPI Master NSS NPCS0 NPCS1 NPCS2 NPCS3 1-of-n Decoder/Demultiplexer 27.7.3.
27.7.3.9 Peripheral Deselection with PDC When the Peripheral DMA Controller is used, the chip select line will remain low during the whole transfer since the TDRE flag is managed by the PDC itself. The reloading of the SPI_TDR by the PDC is done as soon as TDRE flag is set to one. In this case the use of CSAAT bit might not be needed.
SAM3N Figure 27-11. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT NPCS[0..3] DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE DLYBCT NPCS[0..3] DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write SPI_TDR TDRE DLYBCT NPCS[0..3] DLYBCT A B A B DLYBCS DLYBCS PCS = B PCS = B Write SPI_TDR CSAAT = 0 and CSNAAT = 0 CSAAT = 0 and CSNAAT = 1 DLYBCT DLYBCT TDRE NPCS[0..
27.7.3.10 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. In this case, multi-master configuration, NPCS0, MOSI, MISO and SPCK pins must be configured in open drain (through the PIO controller).
SAM3N Figure 27-12.
27.7.5 Write Protected Registers To prevent any single software error that may corrupt SPI behavior, the registers listed below can be write-protected by setting the SPIWPEN bit in the SPI Write Protection Mode Register (SPI_WPMR). If a write access in a write-protected register is detected, then the SPIWPVS flag in the SPI Write Protection Status Register (SPI_WPSR) is set and the field SPIWPVSRC indicates in which register the write access has been attempted.
SAM3N 27.8 Serial Peripheral Interface (SPI) User Interface Table 27-5.
27.8.1 Name: SPI Control Register SPI_CR Address: 0x40008000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI.
SAM3N 27.8.2 Name: SPI Mode Register SPI_MR Address: 0x40008004 Access: Read-write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – WDRBT MODFDIS – PCSDEC PS MSTR • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. • PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select.
• LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.) • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0).
SAM3N 27.8.3 Name: SPI Receive Data Register SPI_RDR Address: 0x40008008 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. • PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer.
SAM3N 27.8.4 Name: SPI Transmit Data Register SPI_TDR Address: 0x4000800C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
SAM3N 27.8.
SAM3N • TXBUFE: TX Buffer Empty 0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. • NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.
SAM3N 27.8.6 Name: SPI Interrupt Enable Register SPI_IER Address: 0x40008014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0 = No effect. 1 = Enables the corresponding interrupt.
SAM3N 27.8.7 Name: SPI Interrupt Disable Register SPI_IDR Address: 0x40008018 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0 = No effect. 1 = Disables the corresponding interrupt.
SAM3N 27.8.8 Name: SPI Interrupt Mask Register SPI_IMR Address: 0x4000801C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
SAM3N 27.8.9 Name: SPI Chip Select Register SPI_CSRx[x=0..3] Address: 0x40008030 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS Note: 3 2 1 0 CSAAT CSNAAT NCPHA CPOL SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the translated value unless the register is written.
SAM3N • BITS: Bits Per Transfer (See the (Note:) below the register table; Section 27.8.9 “SPI Chip Select Register” on page 458.) The BITS field determines the number of data bits transferred. Reserved values should not be used.
SAM3N • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers.
SAM3N 27.8.
SAM3N 27.8.
SAM3N 28. Two-wire Interface (TWI) 28.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
28.
SAM3N 28.4 Block Diagram Figure 28-1. Block Diagram APB Bridge TWCK PIO PMC MCK TWD Two-wire Interface TWI Interrupt 28.5 NVIC Application Block Diagram Figure 28-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 28.5.1 I/O Lines Description Table 28-3.
28.6 28.6.1 Product Dependencies I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 28-2 on page 465). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines.
SAM3N 28.7 28.7.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 28-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 28-3). • A high-to-low transition on the TWD line while TWCK is high defines the START condition.
28.8 Master Mode 28.8.1 Definition The Master is the device that starts a transfer, generates a clock and stops it. 28.8.2 Application Block Diagram Figure 28-5. Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 28.8.
SAM3N After a Master Write transfer, the Serial Clock line is stretched (tied low) while no new data is written in the TWI_THR or until a STOP command is performed. See Figure 28-6, Figure 28-7, and Figure 28-8. Figure 28-6. Master Write with One Data Byte STOP Command sent (write in TWI_CR) S TWD DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 28-7.
Figure 28-8. Master Write with One Byte Internal Address and Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A IADR A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent TXRDY is used as Transmit Ready for the PDC transmit channel. 28.8.5 Master Receiver Mode The read sequence begins by setting the START bit.
SAM3N Figure 28-10. Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read RXRDY is used as Receive Ready for the PDC receive channel. 28.8.6 28.8.6.
Figure 28-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address S TWD DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A W A IADR(15:8) A IADR(7:0) A DATA A W A IADR(7:0) A DATA A DATA A P Two bytes internal address S TWD DADR P One byte internal address S TWD DADR P Figure 28-12.
SAM3N 28.8.7 Using the Peripheral DMA Controller (PDC) The use of the PDC significantly reduces the CPU load. To assure correct implementation, respect the following programming sequences: 28.8.7.1 Data Transmit with the PDC 1. Initialize the transmit PDC (memory pointers, size, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC TXTEN bit. 4. Wait for the PDC end TX flag. 5. Disable the PDC by setting the PDC TXDIS bit. 28.8.7.
28.8.10 Read-write Flowcharts The following flowcharts shown in Figure 28-16 on page 475, Figure 28-17 on page 476, Figure 28-18 on page 477, Figure 28-19 on page 478 and Figure 28-20 on page 479 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 28-15.
SAM3N Figure 28-16.
Figure 28-17.
SAM3N Figure 28-18.
Figure 28-19.
SAM3N Figure 28-20.
28.9 Multi-master Mode 28.9.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
SAM3N Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR. Figure 28-21.
Figure 28-23.
SAM3N 28.10 Slave Mode 28.10.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 28.10.2 Application Block Diagram Figure 28-24. Slave Mode Typical Application Block Diagram VDD R Master Host with TWI Interface 28.10.
Note that a STOP or a repeated START always follows a NACK. See Figure 28-25 on page 485. 28.10.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected.
SAM3N Figure 28-25. Read Access Ordered by a MASTER SADR matches, TWI answers with an ACK SADR does not match, TWI answers with a NACK TWD S ADR R NA DATA NA P/S/Sr SADR R A DATA A ACK/NACK from the Master A DATA NA S/Sr TXRDY Read RHR Write THR NACK SVACC SVREAD SVREAD has to be taken into account only while SVACC is active EOSVACC Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2.
28.10.5.3 General Call The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of General Call, it is up to the programmer to decode the commands which come afterwards. In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches. Figure 28-27 on page 486 describes the General Call access. Figure 28-27.
SAM3N 28.10.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded.
Clock Synchronization in Write Mode The c lock is tied lo w if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 28-29 on page 488 describes the clock synchronization in Read mode. Figure 28-29.
SAM3N 28.10.5.5 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 28-30 on page 489 describes the repeated start + reversal from Read to Write mode. Figure 28-30.
28.10.6 Read Write Flowcharts The flowchart shown in Figure 28-32 on page 490 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 28-32.
SAM3N 28.11 Two-wire Interface (TWI) User Interface Table 28-6.
28.11.1 Name: TWI Control Register TWI_CR Addresses: 0x40018000 (0), 0x4001C000 (1) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 QUICK 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
SAM3N • SVEN: TWI Slave Mode Enabled 0 = No effect. 1 = If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. • SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBUS Quick Command 0 = No effect.
28.11.
SAM3N 28.11.3 Name: TWI Slave Mode Register TWI_SMR Addresses: 0x40018008 (0), 0x4001C008 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode.
28.11.4 Name: TWI Internal Address Register TWI_IADR Addresses: 0x4001800C (0), 0x4001C00C (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
SAM3N 28.11.5 Name: TWI Clock Waveform Generator Register TWI_CWGR Addresses: 0x40018010 (0), 0x4001C010 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV TWI_CWGR is only used in Master mode.
28.11.6 Name: TWI Status Register TWI_SR Addresses: 0x40018020 (0), 0x4001C020 (1) Access: Read-only Reset: 0x0000F009 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame.
SAM3N TXRDY used in Slave mode: 0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it.
1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI. • ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration.
SAM3N 28.11.
28.11.
SAM3N 28.11.
28.11.10 TWI Receive Holding Register Name: TWI_RHR Addresses: 0x40018030 (0), 0x4001C030 (1) Access: Reset: Read-only 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Master or Slave Receive Holding Data 28.11.
SAM3N 29. Universal Asynchronous Receiver Transceiver (UART) 29.1 Description The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. Moreover, the association with two peripheral DMA controller (PDC) channels permits packet handling for these tasks with processor time reduced to a minimum. 29.
29.3 Block Diagram Figure 29-1. UART Functional Block Diagram Peripheral Bridge Peripheral DMA Controller APB UART UTXD Transmit Power Management Controller Parallel Input/ Output Baud Rate Generator MCK Receive URXD Interrupt Control Table 29-1. UART Pin Description Pin Name Description Type URXD UART Receive Data Input UTXD UART Transmit Data Output 29.4 29.4.1 uart_irq Product Dependencies I/O Lines The UART pins are multiplexed with PIO lines.
SAM3N 29.4.3 29.5 Interrupt Source The UART interrupt line is connected to one of the interrupt sources of the Nested Vectored Interrupt Controller (NVIC). Interrupt handling requires programming of the NVIC before configuring the UART. UART Operations The UART operates in asynchronous mode only and supports only 8-bit character handling (with parity). It has no clock pin. The UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator.
The programmer can also put the receiver in its reset state by writing UART_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost. 29.5.2.2 Start Detection and Data Sampling The UART only supports asynchronous operations, and this affects only its receiver.
SAM3N Figure 29-5. Receiver Ready S URXD D0 D1 D2 D3 D4 D5 D6 D7 D0 S P D1 D2 D3 D4 D5 D6 D7 P RXRDY Read UART_RHR 29.5.2.4 Receiver Overrun If UART_RHR has not been read by the software (or the Peripheral Data Controller or DMA Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in UART_SR is set. OVRE is cleared when the software writes the control register UART_CR with the bit RSTSTA (Reset Status) at 1.
Figure 29-8. Receiver Framing Error URXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY FRAME Stop Bit Detected at 0 29.5.3 29.5.3.1 RSTSTA Transmitter Transmitter Reset, Enable and Disable After device reset, the UART transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register UART_CR with the bit TXEN at 1.
SAM3N Register. The TXRDY bit remains high until a second character is written in UART_THR. As soon as the first character is completed, the last character written in UART_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and UART_THR are empty, i.e., all the characters written in UART_THR have been processed, the TXEMPTY bit rises after the last stop bit has been completed. Figure 29-10.
Figure 29-11.
SAM3N 29.6 Universal Asynchronous Receiver Transmitter (UART) User Interface Table 29-3.
29.6.1 Name: UART Control Register UART_CR Addresses: 0x400E0600 (0), 0x400E0800 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
SAM3N 29.6.
29.6.
SAM3N 29.6.
29.6.
SAM3N 29.6.6 Name: UART Status Register UART_SR Addresses: 0x400E0614 (0), 0x400E0814 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the UART_RHR or the receiver is disabled.
1 = There are no characters in UART_THR and there are no characters being processed by the transmitter. • TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active.
SAM3N 29.6.7 Name: UART Receiver Holding Register UART_RHR Addresses: 0x400E0618 (0), 0x400E0818 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set. 29.6.
29.6.
SAM3N 30. Universal Synchronous Asynchronous Receiver Transmitter (USART) 30.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
30.3 Block Diagram Figure 30-1. USART Block Diagram (Peripheral) DMA Controller Channel Channel PIO Controller USART RXD Receiver RTS Interrupt Controller USART Interrupt TXD Transmitter CTS PMC MCK DIV SCK Baud Rate Generator MCK/DIV User Interface SLCK APB Table 30-1.
SAM3N 30.4 Application Block Diagram Figure 30-2.
30.5 I/O Lines Description Table 30-2.
SAM3N 30.6 30.6.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
30.7 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: • 5- to 9-bit full-duplex asynchronous serial communication – MSB- or LSB-first – 1, 1.
SAM3N 30.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.
Baud Rate Calculation Example Table 30-5 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 30-5. Baud Rate Example (OVER = 0) Source Clock Expected Baud Rate MHz Bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.
SAM3N clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: SelectedClock Baudrate = ---------------------------------------------------------------⎛ 8 ( 2 – Over ) ⎛ CD + FP ⎞⎞ -----⎝ ⎝ 8 ⎠⎠ The modified architecture is presented below: Figure 30-4.
where: • B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor • f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 30-6. Table 30-6. Binary and Decimal Values for Di DI field 0001 0010 0011 0100 0101 0110 1000 1001 1 2 4 8 16 32 12 20 Di (decimal) Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 30-7. Table 30-7.
SAM3N Figure 30-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 30.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled.
Figure 30-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed.
SAM3N transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 30-8 and Figure 30-9 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 30-8.
Figure 30-10. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit 30.7.3.4 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set.
SAM3N 30.7.3.5 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 538. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the character data bit is even, and to 1 if the number of 1s is odd.
Figure 30-12. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 30.7.3.6 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit to 0 and addresses are transmitted with the parity bit to 1.
SAM3N Figure 30-13. Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Table 30-10 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 30-10. Maximum Timeguard Length Depending on Baud Rate 30.7.3.8 Baud Rate Bit time Timeguard Bit/sec µs ms 1 200 833 212.
on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. • Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit to 1. If RETTO is performed, the counter starts counting down immediately from the value TO.
SAM3N Table 30-11. Maximum Time-out Period (Continued) 30.7.3.9 Baud Rate Bit Time Time-out 56000 18 1 170 57600 17 1 138 200000 5 328 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR).
The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is to 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with both STTBRK and STPBRK bits to 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored.
SAM3N Figure 30-17. Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2.
30.7.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode (Only on USART0). This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 30.7.4.
SAM3N If no parity error is detected, the I/O line remains to 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 30-21. If a parity error is detected by the receiver, it drives the I/O line to 0 during the guard time, as shown in Figure 30-22. This error bit is also named NACK, for Non Acknowledge.
When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit to 1. Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter.
SAM3N • Configure the TXD pin as PIO and set it as an output to 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption). • Receive data 30.7.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 30-12. Table 30-12. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 Kb/s 78.13 µs 9.6 Kb/s 19.
SAM3N Table 30-13. IrDA Baud Rate Error (Continued) Peripheral Clock 30.7.5.3 Baud Rate CD Baud Rate Error Pulse Time 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.
SAM3N 30.7.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 30-26. Figure 30-26.
SAM3N 30.7.7 SPI Mode The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
SAM3N In SPI Master Mode: • the external clock SCK must not be selected (USCLKS ≠ 0x3), and the bit CLKO must be set to “1” in the Mode Register (US_MR), in order to generate correctly the serial clock on the SCK pin. • to obtain correct behavior of the receiver and the transmitter, the value programmed in CD must be superior or equal to 6.
SAM3N 30.7.7.3 Data Transfer Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). The 9 bits are selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI Mode (Master or Slave).
SAM3N Figure 30-28. SPI Transfer Format (CPHA=1, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 6 5 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master ->TXD SPI Slave -> RXD MISO SPI Master ->RXD SPI Slave -> TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS Figure 30-29.
SAM3N 30.7.7.5 Character Transmission The characters are sent by writing in the Transmit Holding Register (US_THR). An additional condition for transmitting a character can be added when the USART is configured in SPI master mode. In the USART_MR register, the value configured on INACK field can prevent any character transmission (even if US_THR has been written) while the receiver side is not ready (character not read). When INACK equals 0, the character is transmitted whatever the receiver status.
SAM3N 30.7.7.7 30.7.8 Receiver Timeout Because the receiver baudrate clock is active only during data transfers in SPI Mode, a receiver timeout is impossible in this mode, whatever the Time-out value is (field TO) in the Time-out Register (US_RTOR).
SAM3N 30.7.8.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 30-32. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 30-32. Local Loopback Mode Configuration RXD Receiver 1 Transmitter 30.7.8.4 TXD Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 30-33.
SAM3N 30.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 30-15.
SAM3N 30.8.1 Name: USART Control Register US_CR Addresses: 0x40024000 (0), 0x40028000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS/RCS 18 RTSEN/FCS 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter.
SAM3N • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, UNRE and RXBRK in US_CSR. • STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.
SAM3N • RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1. • RCS: Release SPI Chip Select – Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): RCS = 0: No effect. RCS = 1: Releases the Slave Select Line NSS (RTS pin).
SAM3N 30.8.2 Name: USART Mode Register US_MR Addresses: 0x40024004 (0), 0x40028004 (1) Access: Read-write 31 – 30 – 29 – 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 INVDATA 22 – 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF/CPOL 15 14 13 12 11 10 PAR 9 8 SYNC/CPHA 4 3 2 1 0 CHMODE 7 NBSTOP 6 5 CHRL USCLKS USART_MODE This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 577.
SAM3N • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. • CPHA: SPI Clock Phase – Applicable if USART operates in SPI Mode (USART_MODE = 0xE or 0xF): CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured.
SAM3N CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required clock/data relationship between master and slave devices. • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling.
SAM3N 30.8.3 Name: USART Interrupt Enable Register US_IER Addresses: 0x40024008 (0), 0x40028008 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY 0: No effect 1: Enables the corresponding interrupt.
SAM3N 30.8.4 Name: USART Interrupt Disable Register US_IDR Addresses: 0x4002400C (0), 0x4002800C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY 0: No effect 1: Disables the corresponding interrupt.
SAM3N 30.8.5 Name: USART Interrupt Mask Register US_IMR Addresses: 0x40024010 (0), 0x40028010 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
SAM3N 30.8.6 Name: USART Channel Status Register US_CSR Addresses: 0x40024014 (0), 0x40028014 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CTS 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY • RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled.
SAM3N • PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
SAM3N 30.8.7 Name: USART Receive Holding Register US_RHR Addresses: 0x40024018 (0), 0x40028018 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
SAM3N 30.8.8 Name: USART Transmit Holding Register US_THR Addresses: 0x4002401C (0), 0x4002801C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
SAM3N 30.8.9 Name: USART Baud Rate Generator Register US_BRGR Addresses: 0x40024020 (0), 0x40028020 (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 577.
SAM3N 30.8.10 Name: USART Receiver Time-out Register US_RTOR Addresses: 0x40024024 (0), 0x40028024 (1) Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 577. • TO: Time-out Value 0: The Receiver Time-out is disabled.
SAM3N 30.8.11 Name: USART Transmitter Timeguard Register US_TTGR Addresses: 0x40024028 (0), 0x40028028 (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 577. • TG: Timeguard Value 0: The Transmitter Timeguard is disabled.
SAM3N 30.8.12 Name: USART FI DI RATIO Register US_FIDI Addresses: 0x40024040 (0), 0x40028040 (1) Access: Read-write Reset Value: 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 577.
SAM3N 30.8.13 Name: USART Number of Errors Register US_NER Addresses: 0x40024044 (0), 0x40028044 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
SAM3N 30.8.14 Name: USART IrDA FILTER Register US_IF Addresses: 0x4002404C (0), 0x4002804C (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 577. • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
SAM3N 30.8.15 Name: USART Write Protect Mode Register US_WPMR Addresses: 0x400240E4 (0), 0x400280E4 (1) Access: Read-write Reset: See Table 30-15 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII).
SAM3N 30.8.16 Name: USART Write Protect Status Register US_WPSR Addresses: 0x400240E8 (0), 0x400280E8 (1) Access: Read-only Reset: See Table 30-15 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the US_WPSR register.
SAM3N 31. Timer Counter (TC) 31.1 Description The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
– Quadrature Decoder Logic – 2-bit Gray Up/Down Count for Stepper Motor • Each Channel is User-configurable and Contains: – Three External Clock Inputs – Five Internal Clock Inputs – Two Multi-purpose Input/Output Signals • Internal Interrupt Signal • Two Global Registers that Act on All Three TC Channels • Configuration Registers can be write protected 580 SAM3N 11011B–ATARM–21-Feb-12
SAM3N 31.3 Block Diagram Figure 31-1.
31.4 31.5 31.5.1 Pin Name List Pin Name Description Type TCLK0-TCLK2 External Clock Input Input TIOA0-TIOA2 I/O Line A I/O TIOB0-TIOB2 I/O Line B I/O Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 31-3.
SAM3N 31.6 Functional Description 31.6.1 TC Description The three channels of the Timer Counter are independent and identical in operation except when quadrature decoder is enabled. The registers for channel programming are listed in Table 31-4 on page 603. 31.6.2 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock.
Figure 31-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK0 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 31-3.
SAM3N 31.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 31-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. The following triggers are common to both modes: • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. • SYNC: Each channel has a synchronization signal SYNC.
11011B–ATARM–21-Feb-12 MTIOA MTIOB 1 ABETRG CLKI If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel BURST MCK Synchronous Edge Detection RESET LDRB Edge Detector Edge Detector If RA is Loaded CPCTRG OVF Capture Register A LDBSTOP R S CLKEN LDRA Trig CLK S R 16-bit Counter Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS Compar
31.6.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
11011B–ATARM–21-Feb-12 TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST ENETRG CLKI Timer/Counter Channel Edge Detector EEVTEDG SWTRG MCK Synchronous Edge Detection Trig CLK R S OVF WAVSEL RESET 16-bit Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller O
31.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 31-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 31-8. RC Compare cannot be programmed to generate a trigger in this configuration.
SAM3N Figure 31-8. WAVSEL= 00 with trigger Counter cleared by compare match with 0xFFFF Counter Value 0xFFFF Counter cleared by trigger RC RB RA Time Waveform Examples TIOB TIOA 31.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 31-9.
Figure 31-10. WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Time Waveform Examples TIOB TIOA 31.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 31-11. A trigger such as an external event or a software trigger can modify TC_CV at any time.
SAM3N Figure 31-11. WAVSEL = 01 Without Trigger Counter decremented by compare match with 0xFFFF Counter Value 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 31-12. WAVSEL = 01 With Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF Counter decremented by trigger RC RB Counter incremented by trigger RA Waveform Examples Time TIOB TIOA 31.6.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC.
Figure 31-13. WAVSEL = 11 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB RA Time Waveform Examples TIOB TIOA Figure 31-14.
SAM3N 31.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
Interruptions can be generated on different events. A compare function (using TC_RC register) is available on channel 0 (speed/position) or channel 1 (rotation) and can generate an interrupt by means of the CPCS flag in the TC_SR registers. Figure 31-15.
SAM3N By means of the MAXFILT field in TC_BMR, it is possible to configure a minimum duration for which the pulse is stated as valid. When the filter is active, pulses with a duration lower than MAXFILT+1 * tMCK ns are not passed to down-stream logic. Filters can be disabled using the FILTER field in the TC_BMR register. Figure 31-16.
Figure 31-17.
SAM3N 31.6.14.3 Direction Status and Change Detection After filtering, the quadrature signals are analyzed to extract the rotation direction and edges of the 2 quadrature signals detected in order to be counted by timer/counter logic downstream. The direction status can be directly read at anytime on TC_QISR register. The polarity of the direction flag status depends on the configuration written in TC_BMR register. INVA, INVB, INVIDX, SWAP modify the polarity of DIR flag.
A quadrature error is also reported by the quadrature decoder logic. Rather than reporting an error only when 2 edges occur at the same time on PHA and PHB, which is unlikely to occur in real life, there is a report if the time difference between 2 edges on PHA, PHB is lower than a predefined value. This predefined value is configurable and corresponds to (MAXFILT+1) * tMCK ns. After being filtered there is no reason to have 2 edges closer than (MAXFILT+1) * tMCK ns under normal mode of operation.
SAM3N In parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on the TC_CV0 register. Therefore, the accurate position can be read on both TC_CV registers and concatenated to form a 32-bit word. The timer/counter channel 0 is cleared for each increment of IDX count value. Depending on the quadrature signals, the direction is decoded and allows to count up or down in timer/counter channels 0 and 1. The direction status is reported on TC_QISR register. 31.6.14.
Figure 31-20. 2-bit Gray Up/Down Counter. WAVEx = GCENx =1 TIOAx TC_RCx TIOBx DOWNx 31.6.16 Write Protection System In order to bring security to the Timer Counter, a write protection system has been implemented. The write protection mode prevent the write of TC_BMR, TC_CMRx, TC_SMMRx, TC_RAx, TC_RBx, TC_RCx registers. When this mode is enabled and one of the protected registers write, the register write request canceled.
SAM3N 31.7 Timer Counter (TC) User Interface Table 31-4.
31.7.1 Name: TC Block Control Register TC_BCR Addresses: 0x400100C0 (0), 0x400140C0 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC • SYNC: Synchro Command 0 = no effect. 1 = asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
SAM3N 31.7.2 Name: TC Block Mode Register TC_BMR Addresses: 0x400100C4 (0), 0x400140C4 (1) Access: Read-write 31 30 29 28 27 26 – – – – – – 23 22 21 20 19 18 17 16 FILTER – IDXPHB SWAP MAXFILT 25 24 MAXFILT 15 14 13 12 11 10 9 8 INVIDX INVB INVA EDGPHA QDTRANS SPEEDEN POSEN QDEN 7 6 5 4 3 2 1 – – TC2XC2S TC1XC1S 0 TC0XC0S This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 612.
• POSEN: POSition ENabled 0 = disable position. 1 = enables the position measure on channel 0 and 1 • SPEEDEN: SPEED ENabled 0 = disabled. 1 = enables the speed measure on channel 0, the time base being provided by channel 2. • QDTRANS: Quadrature Decoding TRANSparent 0 = full quadrature decoding logic is active (direction change detected). 1 = quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed.
SAM3N 31.7.3 Name: TC Channel Control Register TC_CCRx [x=0..2] Addresses: 0x40010000 (0)[0], 0x40010040 (0)[1], 0x40010080 (0)[2], 0x40014000 (1)[0], 0x40014040 (1)[1], 0x40014080 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0 = no effect.
31.7.4 Name: TC QDEC Interrupt Enable Register TC_QIER Addresses: 0x400100C8 (0), 0x400140C8 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – QERR DIRCHG IDX • IDX: InDeX 0 = no effect. 1 = enables the interrupt when a rising edge occurs on IDX input. • DIRCHG: DIRection CHanGe 0 = no effect.
SAM3N 31.7.5 Name: TC QDEC Interrupt Disable Register TC_QIDR Addresses: 0x400100CC (0), 0x400140CC (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – QERR DIRCHG IDX • IDX: InDeX 0 = no effect. 1 = disables the interrupt when a rising edge occurs on IDX input. • DIRCHG: DIRection CHanGe 0 = no effect.
31.7.6 Name: TC QDEC Interrupt Mask Register TC_QIMR Addresses: 0x400100D0 (0), 0x400140D0 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – QERR DIRCHG IDX • IDX: InDeX 0 = the interrupt on IDX input is disabled. 1 = the interrupt on IDX input is enabled.
SAM3N 31.7.7 Name: TC QDEC Interrupt Status Register TC_QISR Addresses: 0x400100D4 (0), 0x400140D4 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – DIR 7 6 5 4 3 2 1 0 – – – – – QERR DIRCHG IDX • IDX: InDeX 0 = no Index input change since the last read of TC_QISR. 1 = the IDX input has change since the last read of TC_QISR.
31.7.8 Name: TC Write Protect Mode Register TC_WPMR Addresses: 0x400100E4 (0), 0x400140E4 (1) Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0 = disables the Write Protect if WPKEY corresponds to 0x54494D (“TIM” in ASCII). 1 = enables the Write Protect if WPKEY corresponds to 0x54494D (“TIM” in ASCII).
SAM3N 31.7.9 Name: TC Channel Mode Register: Capture Mode TC_CMRx [x=0..
• LDBDIS: Counter Clock Disable with RB Loading 0 = counter clock is not disabled when RB loading occurs. 1 = counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger.
SAM3N 31.7.10 Name: TC Channel Mode Register: Waveform Mode TC_CMRx [x=0..
• CPCDIS: Counter Clock Disable with RC Compare 0 = counter clock is not disabled when counter reaches RC. 1 = counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • EEVT: External Event Selection Signal selected as external event.
SAM3N • ACPA: RA Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ACPC: RC Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • AEEVT: External Event Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ASWTRG: Software Trigger Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggl
• BCPC: RC Compare Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BEEVT: External Event Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BSWTRG: Software Trigger Effect on TIOB 618 Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle SAM3N 11011B–ATARM–21-Feb-12
SAM3N 31.7.11 Name: TC Stepper Motor Mode Register TC_SMMRx [x=0..
31.7.12 Name: TC Counter Value Register TC_CVx [x=0..2] Addresses: 0x40010010 (0)[0], 0x40010050 (0)[1], 0x40010090 (0)[2], 0x40014010 (1)[0], 0x40014050 (1)[1], 0x40014090 (1)[2] Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time. 31.7.13 Name: TC Register A TC_RAx [x=0..
SAM3N 31.7.14 Name: TC Register B TC_RBx [x=0..
31.7.16 Name: TC Status Register TC_SRx [x=0..
SAM3N • ETRGS: External Trigger Status 0 = external trigger has not occurred since the last read of the Status Register. 1 = external trigger has occurred since the last read of the Status Register. • CLKSTA: Clock Enabling Status 0 = clock is disabled. 1 = clock is enabled. • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high.
31.7.17 Name: TC Interrupt Enable Register TC_IERx [x=0..2] Addresses: 0x40010024 (0)[0], 0x40010064 (0)[1], 0x400100A4 (0)[2], 0x40014024 (1)[0], 0x40014064 (1)[1], 0x400140A4 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = no effect.
SAM3N 31.7.18 Name: TC Interrupt Disable Register TC_IDRx [x=0..2] Addresses: 0x40010028 (0)[0], 0x40010068 (0)[1], 0x400100A8 (0)[2], 0x40014028 (1)[0], 0x40014068 (1)[1], 0x400140A8 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = no effect.
31.7.19 Name: TC Interrupt Mask Register TC_IMRx [x=0..
SAM3N 32. Pulse Width Modulation Controller (PWM) 32.1 Description The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.
32.3 Block Diagram Figure 32-1. Pulse Width Modulation Controller Block Diagram PWM Controller PWMx Period Channel PWMx Update Duty Cycle Clock Selector Comparator PWMx Counter PIO PWM0 Channel Period PWM0 Update Duty Cycle Clock Selector PMC MCK Clock Generator Comparator PWM0 Counter APB Interface Interrupt Generator Interrupt Controller APB 32.4 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 32-1. 32.5 32.5.
SAM3N All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs. Table 32-2. 32.5.
32.5.3 Interrupt Sources The PWM interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the PWM interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the PWM interrupt line in edge sensitive mode. Table 32-3. 32.6 Peripheral IDs Instance ID PWM 31 Functional Description The PWM macrocell is primarily composed of a clock generator module and 4 channels.
SAM3N Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC). The PWM macrocell master clock, MCK, is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks.
32.6.2.2 Waveform Properties The different properties of output waveforms are: • the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the PWM_CMRx register. This field is reset at 0. • the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
SAM3N • the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx register. The default mode is left aligned. Figure 32-4. Non Overlapped Center Aligned Waveforms No overlap PWM0 PWM1 Period Note: 1. See Figure 32-5 on page 634 for a detailed description of center aligned waveforms.
Figure 32-5.
SAM3N 32.6.3 32.6.3.1 PWM Controller Operations Initialization Before enabling the output channel, this channel must have been configured by the software application: • Configuration of the clock generator if DIVA and DIVB are required • Selection of the clock for each channel (CPRE field in the PWM_CMRx register) • Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) • Configuration of the period for each channel (CPRD in the PWM_CPRDx register).
Figure 32-6. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 0 1 PWM_CPRDx PWM_CMRx. CPD PWM_CDTYx End of Cycle To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level.
SAM3N 32.6.3.4 Interrupts Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs. A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR register.
32.7 Pulse Width Modulation Controller (PWM) User Interface Table 32-4.
SAM3N 32.7.1 Name: PWM Mode Register PWM_MR Address: 0x40020000 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 PREB 19 18 11 10 DIVB 15 – 14 – 13 – 12 – 7 6 5 4 PREA 3 2 DIVA • DIVA, DIVB: CLKA, CLKB Divide Factor Value Name Description 0 CLK_OFF CLKA, CLKB clock is turned off 1 CLK_DIV1 CLKA, CLKB clock is clock selected by PREA, PREB 2-255 – CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
32.7.2 Name: PWM Enable Register PWM_ENA Address: 0x40020004 Access: Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x. 32.7.
SAM3N 32.7.4 Name: PWM Status Register PWM_SR Address: 0x4002000C Access: Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled.
32.7.5 Name: PWM Interrupt Enable Register PWM_IER Address: 0x40020010 Access: Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x. 32.7.
SAM3N 32.7.7 Name: PWM Interrupt Mask Register PWM_IMR Address: 0x40020018 Access: Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled. 32.7.
32.7.9 Name: PWM Channel Mode Register PWM_CMR[0..
SAM3N 32.7.10 Name: PWM Channel Duty Cycle Register PWM_CDTY[0..3] Addresses: 0x40020204 [0], 0x40020224 [1], 0x40020244 [2], 0x40020264 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 23 22 21 20 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
32.7.11 Name: PWM Channel Period Register PWM_CPRD[0..3] Addresses: 0x40020208 [0], 0x40020228 [1], 0x40020248 [2], 0x40020268 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 23 22 21 20 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD Only the first 16 bits (internal channel counter size) are significant.
SAM3N 32.7.12 Name: PWM Channel Counter Register PWM_CCNT[0..3] Addresses: 0x4002020C [0], 0x4002022C [1], 0x4002024C [2], 0x4002026C [3] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CNT 23 22 21 20 CNT 15 14 13 12 CNT 7 6 5 4 CNT • CNT: Channel Counter Register Internal counter value. This register is reset when: • the channel is enabled (writing CHIDx in the PWM_ENA register).
32.7.13 Name: PWM Channel Update Register PWM_CUPD[0..3] Addresses: 0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CUPD 23 22 21 20 CUPD 15 14 13 12 CUPD 7 6 5 4 CUPD CUPD: Channel Update Register This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle.
SAM3N 33. Analog-to-digital Converter (ADC) 33.1 Description The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to the Block Diagram: Figure 33-1. It also integrates a 16-to-1 analog multiplexer, making possible the analog-to-digital conversions of 16 analog lines. The conversions extend from 0V to ADVREF.
33.3 Block Diagram Figure 33-1. Analog-to-Digital Converter Block Diagram Timer Counter Channels PMC MCK ADC Controller Trigger Selection ADTRG Control Logic ADC Interrupt Interrupt Controller ADC cell ADVREF System Bus PDC User Interface AD- Analog Inputs Multiplexed with I/O lines PIO Peripheral Bridge Successive Approximation Register Analog-to-Digital Converter APB ADCHx AD- GND 33.4 Signal Description Table 33-1.
SAM3N 33.5 Product Dependencies 33.5.1 Power Management The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller MCK in the Power Management Controller (PMC) before using the ADC Controller. However, if the application does not require ADC operations, the ADC Controller clock can be stopped when not needed and restarted when necessary. Configuring the ADC Controller does not require the ADC Controller clock to be enabled. 33.5.
Table 33-3. 33.5.5 I/O Lines ADC AD13 PC29 X1 ADC AD14 PC30 X1 ADC AD15 PC31 X1 Timer Triggers Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the timer counters may be unconnected. 33.5.6 33.6 33.6.1 Conversion Performances For performance and electrical characteristics of the ADC, see the product DC Characteristics section.
SAM3N Figure 33-2. Sequence of ADC conversions ADCClock Trigger event (Hard or Soft) Analog cell IOs ADC_ON ADC_Start ADC_eoc ADC_SEL CH0 LCDR CH1 CH2 CH0 CH1 DRDY Conversion of CH0 Start Up Time (and tracking of CH0) Tracking of CH1 Conversion of CH1 Tracking of CH2 33.6.2 Conversion Reference The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages convert to values based on a linear conversion. 33.6.
Figure 33-3. EOCx and DRDY Flag Behavior Write the ADC_CR with START = 1 Read the ADC_CDRx Write the ADC_CR with START = 1 Read the ADC_LCDR CHx (ADC_CHSR) EOCx (ADC_SR) DRDY (ADC_SR) If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVREx) flag is set in the Overrun Status Register (ADC_OVER). Likewise, new data converted when DRDY is high sets the GOVRE bit (General Overrun Error) in ADC_SR.
SAM3N Figure 33-4.
33.6.5 Conversion Triggers Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the START bit at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the TRGSEL field in the Mode Register (ADC_MR).
SAM3N a Timer/Counter output. The periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the PDC. The sequence can be customized by programming the Sequence Channel Registers, ADC_SEQR1 and ADC_SEQR2 and setting to 1 the USEQ bit of the Mode Register (ADC_MR). The user can choose a specific order of channels and can program up to 16 conversions by sequence.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to program a precise value in the TRACKTIM field. See the product ADC Characteristics section. 33.6.9 Buffer Structure The PDC read channel is triggered each time new data is stored in ADC_LCDR register. The same structure of data is repeatedly stored in ADC_LCDR register each time a trigger event occurs.
SAM3N 33.7 Analog-to-Digital Converter (ADC) User Interface Any offset not listed in Table 33-4 must be considered as “reserved”. Table 33-4.
33.7.1 Name: ADC Control Register ADC_CR Address: 0x40038000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 START 0 SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion.
SAM3N 33.7.2 Name: ADC Mode Register ADC_MR Address: 0x40038004 Access: Read-write 31 USEQ 30 – 29 – 28 – 27 23 – 22 – 21 – 20 – 19 15 14 13 12 11 3 26 25 24 17 16 10 9 8 2 TRGSEL 1 0 TRGEN TRACKTIM 18 STARTUP PRESCAL 7 FREERUN 6 FWUP 5 SLEEP 4 LOWRES This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 677. • TRGEN: Trigger Enable Value Name Description 0 DIS Hardware triggers are disabled.
• FWUP: Fast Wake Up Value Name Description 0 OFF Normal Sleep Mode: The sleep mode is defined by the SLEEP bit 1 ON Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF • FREERUN: Free Run Mode Value Name Description 0 OFF Normal Mode 1 ON Free Run Mode: Never wait for any trigger.
SAM3N 33.7.3 Name: ADC Channel Sequence 1 Register ADC_SEQR1 Address: 0x40038008 Access: Read-write 31 30 29 28 27 26 USCH8 23 22 21 14 20 19 18 13 6 17 16 9 8 1 0 USCH5 12 11 10 USCH4 7 24 USCH7 USCH6 15 25 USCH3 5 4 USCH2 3 2 USCH1 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 677.
33.7.4 Name: ADC Channel Sequence 2 Register ADC_SEQR2 Address: 0x4003800C Access: Read-write 31 30 29 28 27 26 USCH16 23 22 21 14 20 19 18 13 6 17 16 9 8 1 0 USCH13 12 11 10 USCH12 7 24 USCH15 USCH14 15 25 USCH11 5 4 USCH10 3 2 USCH9 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 677.
SAM3N 33.7.5 Name: ADC Channel Enable Register ADC_CHER Address: 0x40038010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 677. • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel.
33.7.6 Name: ADC Channel Disable Register ADC_CHDR Address: 0x40038014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 677. • CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel.
SAM3N 33.7.7 Name: ADC Channel Status Register ADC_CHSR Address: 0x40038018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled.
33.7.8 Name: ADC Last Converted Data Register ADC_LCDR Address: 0x40038020 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 1 0 CHNB 7 6 LDATA 5 4 3 2 LDATA • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
SAM3N 33.7.
33.7.
SAM3N 33.7.
33.7.12 Name: ADC Interrupt Status Register ADC_ISR Address: 0x40038030 Access: Read-only 31 – 30 – 29 – 28 RXBUFF 27 ENDRX 26 COMPE 25 GOVRE 24 DRDY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 EOC15 14 EOC14 13 EOC13 12 EOC12 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished.
SAM3N 33.7.13 Name: ADC Overrun Status Register ADC_OVER Address: 0x4003803C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 OVRE15 14 OVRE14 13 OVRE13 12 OVRE12 11 OVRE11 10 OVRE10 9 OVRE9 8 OVRE8 7 OVRE7 6 OVRE6 5 OVRE5 4 OVRE4 3 OVRE3 2 OVRE2 1 OVRE1 0 OVRE0 • OVREx: Overrun Error x 0 = No overrun error on the corresponding channel since the last read of ADC_OVER.
33.7.14 Name: ADC Extended Mode Register ADC_EMR Address: 0x40038040 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 TAG 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 CMPALL 8 – 7 6 5 4 3 – 2 – 1 0 CMPSEL CMPMODE This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 677.
SAM3N 33.7.15 Name: ADC Compare Window Register ADC_CWR Address: 0x40038044 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 HIGHTHRES 19 18 17 16 11 10 9 8 1 0 HIGHTHRES 15 – 14 – 13 – 12 – 7 6 5 4 LOWTHRES 3 2 LOWTHRES This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 677. • LOWTHRES: Low Threshold Low threshold associated to compare settings of ADC_EMR register.
33.7.16 Name: ADC Channel Data Register ADC_CDRx [x=0..15] Address: 0x40038050 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 DATA 0 DATA • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
SAM3N 33.7.17 Name: Address: ADC Write Protect Mode Register ADC_WPMR 0x400380E4 Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
33.7.18 Name: ADC Write Protect Status Register ADC_WPSR Address: 0x400380E8 Access: Read-only 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the ADC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the ADC_WPSR register.
SAM3N 34. Digital to Analog Converter Controller (DACC) 34.1 Description The Digital-to-Analog Converter Controller (DACC) has one analog output, making it possible for the digital-to-analog conversion to drive one analog line. The DACC supports 10-bit resolution and data to be converted are sent in a common register. External triggers, through the ext_trig pins, or internal triggers are configurable. The DACC Controller connects with a PDC channel. This feature reduces processor intervention.
34.3 Block Diagram Figure 34-1.
34.4 Signal Description Table 34-1. DAC Pin Description Pin Name Description DAC0 Analog output channel DATRG External triggers 34.5 Product Dependencies 34.5.1 Power Management The DAC can be enabled and disabled through the DACEN bit of the DACC Mode Register. 34.5.2 Interrupt Sources The DACC interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the DACC interrupt requires the Interrupt Controller to be programmed first. Table 34-2. 34.5.
34.6 Functional Description 34.6.1 Digital-to-analog Conversion The DAC uses the master clock (MCK) to perform conversions. Once a conversion has started, the DAC will take a setup time to provide the analog result on the analog output. Refer to the product electrical characteristics for more information. 34.6.2 Conversion Results When a conversion is completed, the resulting analog value is available at the DAC channel output. 34.6.
34.6.4 Conversion FIFO To provide flexibility and high efficiency, a 4 half-word FIFO is used to handle the data to be converted. As long as the TXRDY flag in the DACC Interrupt Status Register is active the DAC Controller is ready to accept conversion requests by writing data in the DACC Conversion Data Register (DACC_CDR). Data which cannot be converted immediately are stored in the DACC FIFO. When the FIFO is full or the DACC is not ready to accept conversion requests, the TXRDY flag is inactive.
34.7 Digital-to-Analog Converter Controller (DACC) User Interface Table 34-3.
34.7.1 Name: DACC Control Register DACC_CR Address: 0x4003C000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the DACC simulating a hardware reset.
34.7.2 Name: DACC Mode Register DACC_MR Address: 0x4003C004 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 TRGSEL 1 0 TRGEN CLKDIV 23 22 21 20 CLKDIV 15 14 13 12 STARTUP 7 – 6 – 5 WORD 4 DACEN • TRGEN: Trigger Enable TRGEN Selected Mode 0 External trigger mode disabled. DACC in free running mode. 1 External trigger mode enabled.
• STARTUP: Startup Time Selection Startup Time = (STARTUP+1) * Clock period • CLKDIV: DAC Clock Divider for Internal Trigger Trigger Period = CLKDIV * Clock period 687 SAM3N 11011B–ATARM–21-Feb-12
34.7.3 Name: DACC Conversion Data Register DACC_CDR Address: 0x4003C008 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA • DATA: Data to Convert Data to convert. Can be one half-word or two half-word s depending on WORD bit in DACC_MR register.
34.7.4 Name: DACC Interrupt Enable Register DACC_IER Address: 0x4003C00C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TXBUFE 1 ENDTX 0 TXRDY • TXRDY: Transmission Ready Interrupt Enable Enables ready for transmission interrupt. • ENDTX: End of PDC Interrupt Enable • TXBUFE: Buffer Empty Interrupt Enable Enables end of conversion IT.
34.7.5 Name: DACC Interrupt Disable Register DACC_IDR Address: 0x4003C010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TXBUFE 1 ENDTX 0 TXRDY • TXRDY: Transmission Ready Interrupt Disable Disables ready for transmission interrupt.
34.7.
34.7.
34.7.8 Name: DACC Write Protect Mode Register DACC_WPMR Address: 0x4003C0E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444143 (“DAC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444143 (“DAC” in ASCII). Protects the DACC Mode Register.
34.7.9 Name: DACC Write Protect Status Register DACC_WPSR Address: 0x4003C0E8 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 – 0 WPROTERR WPROTADDR 7 – 6 – 5 – 4 – • WPROTERR: Write protection error Indicates a write protection error. • WPROTADDR: Write protection error address Indicates the address of the register write request which generated the error.
SAM3N 35. Electrical Characteristics 35.1 Absolute Maximum Ratings Table 35-1. Absolute Maximum Ratings* Operating Temperature (Industrial) ................-40° C to + 85° C Storage Temperature.....................................-60°C to + 150°C Voltage on Input Pins with Respect to Ground...... ..............................-0.3V to + 4.0V Maximum Operating Voltage (VDDCORE) ......................................................................2.
35.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified Table 35-2. DC Characteristics Symbol Parameter VDDCORE DC Supply Core Conditions (2) (3) Min Typ Max Unit s 1.62 1.8 1.95 V 1.62 3.3 3.6 V 1.62 1.95 V VVDDIO DC Supply I/Os VVDDPLL PLL and Main Oscillator Supply VIL Input Low-level Voltage PA0-PA31, PB0-PB14, PC0-PC31 -0.3 0.
SAM3N Table 35-2. Symbol DC Characteristics (Continued) Parameter IOH (or ISOURCE) Conditions Min Typ 1.62V < VDDIO < 1.95V; VOH = VVDDIO - 0.4 - PA14 (SPCK), pins - PA0-PA3 - Other pins(1) -6 -6 -3 3.0V < VDDIO < 3.6V; VOH = VVDDIO - 0.4 - PA14 (SPCK), pins - PA0-PA3 - Other pins(1) -6 -6 -3 1.62V < VDDIO < 3.6V; VOH = VVDDIO - 0.4 - NRST IOL (or ISINK) Unit s mA -2 Relaxed Mode: 3.0V < VDDIO < 3.6V; VOH = 2.2V - PA14 (SPCK), pins - PA0-PA3 - Other pins(1) IO Max -14 -16 -8 1.
Table 35-3. Symbol 1.8V Voltage Regulator Characteristics Parameter Conditions Min Typ Max Units VVDDIN DC Input Voltage Range (3) (4) 1.8 3.3 3.6 V VVDDOUT DC Output Voltage Normal Mode Standby Mode VACCURACY Output Voltage Accuracy ILoad = 0.5 mA to 60 mA ILOAD Maximum DC Output Current DDROPOUT Dropout Voltage VLINE Line Regulation VLINE-TR Transient Line regulation 1.8 0 -3 3 % VVDDIN > 2V VVDDIN ≤2V 60 40 mA VVDDIN = 1.8V, ILoad = 40 mA 150 mV VVDDIN from 2.7V to 3.
SAM3N Table 35-4. Symbol Core Power Supply Brownout Detector Characteristics Parameter Conditions (1) Min Typ Max Units 1.52 1.55 1.58 V 25 38 mV VTH- Supply Falling Threshold VHYST- Hysteresis VTH- VTH+ Supply Rising Threshold 1.35 1.50 1.
Table 35-5. VDDIO Supply Monitor Symbol Parameter Conditions Min VTH Supply Monitor Threshold 16 selectable steps of 100mV TACCURACY Threshold Level Accuracy VHYST Hysteresis IDDON Current Consumption on VDDCORE IDDOFF Startup Time TSTART Max Units 1.9 3.4 V -1.5 +1.5 % 20 30 mV 18 28 enabled Typ µA disabled 1 From disabled state to enabled state 140 µs Figure 35-2. VDDIO Supply Monitor VDDIO Vth + Vhyst Vth Reset Table 35-6.
SAM3N Table 35-7. Symbol ISB ICC DC Flash Characteristics Parameter Conditions Typ Max Units Standby current @25°C onto VDDCORE = 1.8V @85°C onto VDDCORE = 1.8V @25°C onto VDDCORE = 1.95V @85°C onto VDDCORE = 1.95V 3.2 6 4 6.5 4 8 4.8 9 µA µA µA µA 128-Bit Mode Read Access: Maximum Read Frequency onto VDDCORE = 1.8V @ 25 °C Maximum Read Frequency onto VDDCORE = 1.95V @ 25 °C 19 25 22.5 30 mA mA 64-Bit Mode Read Access: Maximum Read Frequency onto VDDCORE = 1.
35.3 Power Consumption • Power consumption of the device according to the different Low Power Mode Capabilities (Backup, Wait, Sleep) and Active Mode. • Power consumption on power supply in different modes: Backup, Wait, Sleep and Active. • Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 35.3.1 Backup Mode Current Consumption The Backup Mode configuration and measurements are defined as follow. Figure 35-4.
SAM3N Table 35-8. Conditions Total Consumption (AMP1) Configuration A Total Consumption (AMP1) Configuration B VDDIO = 3.3V @25°C VDDIO = 3.0V @25°C VDDIO = 2.5V @25°C VDDIO = 1.8V @25°C 2.85 2.55 2.1 1.56 3.25 2.96 2.50 1.89 µA VDDIO = 3.3V @85°C VDDIO = 3.0V @85°C VDDIO = 2.5V @85°C VDDIO = 1.8V @85°C TBD TBD TBD TBD TBD TBD TBD TBD µA Table 35-9. 35.3.
Table 35-10 gives current consumption in typical conditions. Table 35-10. Typical Current Consumption for Sleep Mode Conditions Figure 35-6 @25°C MCK = 48 MHz There is no activity on the I/Os of the device. VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit 6.4 8.4 mA Figure 35-6. Current Consumption in Sleep Mode (AMP1) versus Master Clock ranges (Conditions from Table 35-10) 9.00 8.00 IDDCORE in mA 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.
SAM3N Table 35-11. Sleep mode Current consumption versus Master Clock (MCK) variation Core Clock/MCK (MHz) 35.3.2.2 VDDCORE Consumption (AMP1) Total Consumption (AMP2) 62 8.16 10.7 48 6.4 8.4 32 4.3 5.65 24 3.5 5.5 12 1.68 1.71 8 1.13 1.16 4 0.56 0.57 2 0.33 0.35 1 0.22 0.23 0.5 0.16 0.17 0.25 0.14 0.16 0.125 0.12 0.13 0.032 0.01 0.02 Unit mA Wait Mode Figure 35-7. Measurement Setup for Wait Mode AMP2 3.
Table 35-12. Typical Current Consumption in Wait Mode Conditions VDDOUT Consumption (AMP1) Total Consumption (AMP2) Unit 5.7 14.9 µA See Figure 35-7 on page 705 @25°C There is no activity on the I/Os of the device. 35.3.3 Active Mode Power Consumption The Active Mode configuration and measurements are defined as follows: • VDDIO = VDDIN = 3.3V • VDDCORE = 1.8V (Internal Voltage regulator used) and 1.
SAM3N 35.3.3.1 Active Power Consumption with VDDCORE @ 1.8V Table 35-13. Master Clock (MCK) and Core Clock variation (SAM3N4/2/1 MRL A) Core Clock /MCK (MHz) AMP1 (VDDOUT) Consumption Division 128-bit Flash access Unit Fibonacci 64-bit Flash access 128-bit Flash access 64-bit Flash access 62 30 25.3 31.4 28.55 48 24.45 20.6 26.2 23.15 32 15.6 14.3 20 17.7 24 11.4 10.5 15.6 15 12 6.45 5.7 9.2 8.5 8 4.9 4.2 7.1 6.4 4 4.3 2.9 4.5 2.9 2 2.2 1.5 2.4 1.7 1 1.1 0.
35.3.3.2 Active Power Consumption with VDDCORE @ 1.62V Table 35-15. Master Clock (MCK) and Core Clock variation (SAM3N4/2/1 MRL A) Core Clock / MCK (MHz) AMP1 (VDDOUT) Consumption Division 128-bit Flash access Unit Fibonacci 64-bit Flash access 128-bit Flash access 64-bit Flash access 62 25.7 22.6 27.05 25.2 48 20.8 18 23.2 20.4 32 14.1 12.5 17.2 15.75 24 11.1 9.25 13.65 13.2 12 5.6 5 7.9 7.36 8 4.2 3.6 5.9 5.41 4 3.55 2.4 3.6 5.5 2 1.84 1.3 1.88 1.3 1 1 0.
SAM3N 35.3.4 Peripheral Power Consumption in Active Mode Table 35-17. Power Consumption on VDDCORE(1) (SAM3N4/2/1 MRL A) Peripheral Consumption (Typ) PIO Controller A (PIOA) 10 PIO Controller B (PIOB) 5.15 PIO Controller C (PIOC) 9.8 UART0 (PDC) 14 UART1 (no PDC) 3.8 USART0 (PDC) 21.2 USART1 (no PDC) 8.2 PWM 10.55 TWI0 (PDC) 15.25 TWI1 (no PDC) 4.6 SPI 12.5 TC0, TC3 9 TC1, TC2, TC4, TC5 5 ADC 17.6 DACC 7.75 Note: Unit µA/MHz 1. Note: VDDIO = 3.3V, VDDCORE = 1.
35.4 Crystal Oscillators Characteristics 35.4.1 32 kHz RC Oscillator Characteristics Table 35-19. 32 kHz RC Oscillator Characteristics Symbol Parameter Conditions RC Oscillator Frequency Frequency Supply Dependency Frequency Temperature Dependency Duty Duty Cycle TON Startup Time IDDON Typ Max Unit 20 32 44 kHz -3 3 %/V -11 11 % 55 % 100 µs 870 nA 45 After Startup Time Temp. Range = -40°C to +85°C Typical Consumption at 2.2V supply and Temp = 25°C Current Consumption 35.4.
SAM3N The 4/8/12 MHz Fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB Bit command (see EEFC section) and the frequency can be trimmed by software through the PMC. Figure 35-9 and Figure 35-10 show the frequency versus trimming for 8 and 12 MHz. Figure 35-9. RC 8 MHz trimming Figure 35-10.
35.4.3 32.768 kHz Crystal Oscillator Characteristics Table 35-21. 32.768 kHz Crystal Oscillator Characteristics Symbol Parameter Conditions Min Freq Operating Frequency Normal mode with crystal Supply Ripple Voltage (on VDDIO) Rms value, 10 KHz to 10 MHz Duty Cycle 40 Rs < 50KΩ Startup Time Rs < 100KΩ (1) Rs < 50KΩ Current consumption Rs < 100KΩ (1) PON Drive level Rf Internal resistor CLEXT Maximum external capacitor on XIN32 and XOUT32 50 Ccrystal = 12.
SAM3N 35.4.5 32.768 kHz XIN32 Clock Input Characteristics in Bypass Mode Table 35-23.
35.4.6 3 to 20 MHz Crystal Oscillator Characteristics Table 35-24. 3 to 20 MHz Crystal Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit Freq Operating Frequency Normal mode with crystal 3 16 20 MHz Freq_bypass Operating Frequency In Bypass Mode External Clock on XIN 50 MHz Supply Ripple Voltage (on VDDPLL) Rms value, 10 KHz to 10 MHz 30 mV 60 % 14.5 4 1.
SAM3N 35.4.7 3 to 20 MHz Crystal Characteristics Table 35-25. Crystal Characteristics Symbol Parameter Conditions ESR Equivalent Series Resistor (Rs) Fundamental @ 3MHz Fundamental @ 8MHz Fundamental @ 12MHz Fundamental @ 16MHz Fundamental @ 20MHz CM CSHUNT 35.4.8 Min Typ Max Unit 200 100 80 80 50 Ω Motional capacitance 8 fF Shunt capacitance 7 pF Max Units 50 MHz 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode Table 35-26.
35.4.9 35.4.9.1 Crystal Oscillators Design Consideration Information Choosing a Crystal When choosing a crystal for the 32768 Hz Slow Clock Oscillator or for the 3-20 MHz Oscillator, several parameters must be taken into account. Important parameters between crystal and SAM3N specifications are as follows: • Load Capacitance – Ccrystal is the equivalent capacitor value the oscillator must “show” to the crystal in order to oscillate at the target frequency.
SAM3N 35.5 PLL Characteristics Table 35-27. Supply Voltage Phase Lock Loop Characteristics Symbol Parameter Conditions Supply Voltage Range VDDPLL Allowable Voltage Ripple Min Typ Max Unit 1.6 1.8 1.95 V 30 10 mV Max Unit RMS Value 10 kHz to 10 MHz RMS Value > 10 MHz Table 35-28. PLL Characteristics Symbol Parameter FIN Input Frequency 3.5 20 MHz FOUT Output Frequency 60 130 MHz 1.7 2.
35.6 10-Bit ADC Characteristics Table 35-29. Analog Power Supply Characteristics Symbol Parameter VVDDIN ADC Analog Supply IVDDIN Active Current Consumption Conditions Min Typ 3.0 on VDDIN 0.55 Max Units 3.6 V 1 mA Table 35-30.
SAM3N . Table 35-33. External Voltage Reference Input Parameter Conditions Min ADVREF Input Voltage Range ADVREF Input Voltage Range 8-bit resolution mode ADVREF Average Current On 13 samples with ADC Clock = 5 MHz Typ Max Units 2.6 VDDIN V 2.5 VDDIN V 200 250 µA Typ Max Units Table 35-34. Analog Inputs Parameter Min Input Voltage Range 0 VADVREF Input Leakage Current Input Capacitance Note: 12 ±1 µA 14 pF 1.
35.7 10-Bit DAC Characteristics Table 35-35. Analog Power Supply Characteristics Symbol Parameter Conditions VVDDIN Analog Supply Active Current Consumption IVDDIN Min Typ Max 3.6 V 485 250 660 300 µA µA Typ Max Units 500 kHz 5 µs 2.4 On VDDIN On ADVREF Units Table 35-36. Channel Conversion Time and DAC Clock Symbol Parameter Conditions FDAC Clock Frequency TSTART-UP Startup time TCONV Conversion Time Min 1 TCP_DAC External voltage reference for DAC is ADVREF.
SAM3N 35.8 AC Characteristics 35.8.1 Master Clock Characteristics Table 35-39. Master Clock Waveform Parameters Symbol Parameter Conditions 1/(tCPMCK) Master Clock Frequency 1/(tCPMCK) Master Clock Frequency 35.8.2 Min Max Units VDDCORE @ 1.62V 48 MHz VDDCORE @ 1.
35.8.3 SPI Characteristics Figure 35-12. SPI Master Mode with (CPOL= NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI1 SPI0 MISO SPI2 MOSI Figure 35-13. SPI Master Mode with (CPOL = 0 and NCPHA=1) or (CPOL=1 and NCPHA= 0) SPCK SPI4 SPI3 MISO SPI5 MOSI Figure 35-14.
SAM3N Figure 35-15. SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1) NPCS0 SPI15 SPI14 SPCK SPI9 MISO SPI10 SPI11 MOSI 35.8.3.1 Maximum SPI Frequency The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write modes. Master Write Mode The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI2 (or SPI5) timing. Since it gives a maximum frequency above the maximum pad speed (see Section 35.8.
35.8.3.2 SPI Timings Table 35-41. SPI Timings Symbol SPI0 SPI1 Parameter MISO Setup time before SPCK rises (master) MISO Hold time after SPCK rises (master) Conditions Min 3.3V domain(1) 14.2 ns (2) 17 ns (1) 3.3V domain 0 ns 1.8V domain(2) 0 ns 1.
SAM3N 35.8.4 USART in SPI Mode Timings Timings are given with the following conditions. VDDIO = 1.62V and 3V SCK/MISO/MOSI Load = 30 pF Figure 35-16. USART SPI Master Mode NSS SPI5 SPI3 CPOL=1 SPI0 SCK CPOL=0 SPI4 MISO SPI4 SPI1 SPI2 LSB MSB MOSI • the MOSI line is driven by the output pin TXD • the MISO line drives the input pin RXD • the SCK line is driven by the output pin SCK • the NSS line is driven by the output pin RTS Figure 35-17.
Figure 35-18. USART SPI Slave mode: (Mode 0 or 3) NSS SPI14 SPI15 SCK SPI9 MISO SPI10 SPI11 MOSI Table 35-42. USART SPI Timings Symbol Parameter Conditions Min Max Units Master Mode SPI0 tCPSCK Period 1.8v domain 3.3v domain tCPMCK /6 ns SPI1 Input Data Setup Time 1.8v domain 3.3v domain 0.5 * tCPMCK + 2.6 0.5 * tCPMCK + 2.4 ns SPI2 Input Data Hold Time 1.8v domain 3.3v domain 1.5 * tCPMCK -0.3 1.5 * tCPMCK -0.3 ns SPI3 Chip Select Active to Serial Clock 1.8v domain 3.
SAM3N Table 35-42. USART SPI Timings (Continued) Symbol Parameter Conditions Min SPI10 MOSI Setup time before tCPSCK falls 1.8v domain 3.3v domain 2 * tCPMCK + 1.8 2 * tCPMCK + 1.7 ns SPI11 MOSI Hold time after tCPSCK falls 1.8v domain 3.3v domain 0.5 0.4 ns SPI12 NPCS0 setup to tCPSCK rising 1.8v domain 3.3v domain 2.5 * tCPMCK -0.26 2.5 * tCPMCK -0.4 ns SPI13 NPCS0 hold after tCPSCK falling 1.8v domain 3.3v domain 1.5 * tCPMCK + 2.2 1.
35.8.5 Two-wire Serial Interface Characteristics Table 35-43 describes the requirements for devices connected to the Two-wire Serial Bus. For timing symbols refer to Figure 35-19. Table 35-43.
SAM3N Figure 35-19. Two-wire Serial Bus Timing tHIGH tof tLOW tr tLOW TWCK tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO TWD tBUF 35.8.6 Embedded Flash Characteristics The maximum operating frequency is given in tables 35-44 and 35-45 below but is limited by the Embedded Flash access time when the processor is fetching code out of it. The tables 35-44 and 35-45 below give the device maximum operating frequency depending on the field FWS of the MC_FMR register.
36. Mechanical Characteristics Figure 36-1. 100-lead LQFP Package Mechanical Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information. Table 36-1. Device and LQFP Package Maximum Weight SAM3N4/2/1 Table 36-2. 800 Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification e3 Table 36-3. mg LQFP Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI User Group.
SAM3N Figure 36-2. 100-ball TFBGA Package Drawing Table 36-4. Soldering Information (Substrate Level) Ball Land TBD Soldering Mask Opening TBD Table 36-5. Device Maximum Weight TBD Table 36-6. mg 100-ball Package Characteristics Moisture Sensitivity Level Table 36-7.
Figure 36-3.
SAM3N Table 36-8. 48-lead LQFP Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC E 9.00 BSC 0.354 BSC E1 7.00 BSC 0.276 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.5° 7° θ1 0° – – 0° – – θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.
Table 36-9. Symbol 64-lead LQFP Package Dimensions (in mm) Millimeter Inch Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 12.00 BSC 0.472 BSC D1 10.00 BSC 0.383 BSC E 12.00 BSC 0.472 BSC E1 10.00 BSC 0.383 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.5° 7° θ1 0° – – 0° – – θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.
SAM3N Figure 36-4.
Table 36-13. 48-pad QFN Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 090 – – 0.035 A1 – – 0.050 – – 0.002 A2 – 0.65 0.70 – 0.026 0.028 A3 b 0.20 REF 0.18 D D2 0.20 0.008 REF 0.23 0.007 7.00 bsc 5.45 E 5.60 0.008 0.009 0.276 bsc 5.75 0.215 7.00 bsc 0.220 0.226 0.276 bsc E2 5.45 5.60 5.75 0.215 0.220 0.226 L 0.35 0.40 0.45 0.014 0.016 0.018 e R 0.50 bsc 0.09 – 0.020 bsc – 0.
SAM3N Figure 36-5.
Table 36-14. 64-pad QFN Package Dimensions (in mm) Symbol Millimeter Inch Min Nom Max Min Nom Max A – – 090 – – 0.035 A1 – – 0.05 – – 0.001 A2 – 0.65 0.70 – 0.026 0.028 A3 b 0.20 REF 0.23 D D2 0.28 0.009 0.010 9.00 bsc 6.95 E 7.10 6.95 L 0.35 e 7.25 0.274 0.280 7.10 7.25 0.274 0.40 0.45 0.014 – 0.285 0.354 bsc 0.50 bsc 0.125 0.011 0.354 bsc 9.00 bsc E2 R 0.25 0.008 REF 0.280 0.285 0.016 0.018 0.020 bsc – 0.
SAM3N 36.1 Soldering Profile Table 36-18 gives the recommended soldering profile from J-STD-020C. Table 36-18. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3° C/sec. max. Preheat Temperature 175°C ±25°C 180 sec. max. Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5° C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260° C Ramp-down Rate 6° C/sec. max. Time 25° C to Peak Temperature 8 min. max.
37. Ordering Information Table 37-1.
SAM3N Table 37-1.
SAM3N 11011B–ATARM–21-Feb-12
SAM3N 38. SAM3N Series Errata 38.1 Marking All devices are marked with the Atmel logo and the ordering code. Additional marking may be in one of the following formats: YYWW V XXXXXXXXX ARM where • “YY”: manufactory year • “WW”: manufactory week • “V”: revision • “XXXXXXXXX”: lot number 38.2 SAM3N4/2/1 Errata - Rev. A Parts Refer to Section 38.1 “Marking”.
38.3 38.3.1 Flash Memory Flash: Flash Programming When writing data into the Flash memory plane (either through the EEFC, using the IAP function or FFPI), the data may not be correctly written (i.e the data written is not the one expected). Problem Fix/Workaround Set the number of Wait States (WS) at 6 (FWS = 6) during the programming. 38.3.
SAM3N 38.4 SAM3N1 Errata - Rev. B Parts / SAM3N0/00 -Rev. A Parts Refer to Section 38.1 “Marking”. Notes: ATSAM3N1C Revision B chip ID is 0x29580561 ATSAM3N1B Revision B chip ID is 0x29480561 ATSAM3N1A Revision B chip ID is 0x29380561 ATSAM3N0C Revision A chip ID is 0x295 80361 ATSAM3N0B Revision A chip ID is 0x294 80361 ATSAM3N0A Revision A chip ID is 0x293 80361 ATSAM3N00B Revision A chip ID is 0x294 50261 ATSAM3N00A Revision A chip ID is 0x293 50261 38.4.
SAM3N 11011B–ATARM–21-Feb-12
SAM3N Revision History Doc. Rev. 11011B Comments Overview: All mentions of 100-ball LFBGA changed into 100-ball TFBGA Numerous updates Section 7. “Product Mapping”, Heading was ‘Memories’. Changed to ‘Product Mapping’ Several updates to clarify that only 1 USART has ISO7816 capability Two typos corrected in chapter 12 and 32 Section 5. “Power Considerations”: Figure 5-5 “Fast Start-Up Sources”, Changed from Edge detection to Level detection. Section 24.
Change Request Ref. Doc. Rev. 11011B Comments ELEC: Section 35.2 “DC Characteristics”: PULLUP Pull-up Resistor NRST: New values added PULLDOWN Pull-down Resistor: Changed signal names and added one line for signal names PB10-PB11 Section 35. “Electrical Characteristics”: Table 35-19, “32 kHz RC Oscillator Characteristics,” , changed parameter ‘Frequency Temperature Dependency’ Table 35-4, “Core Power Supply Brownout Detector Characteristics,” , changed MAX value of VTH+ Section 35.8.
SAM3N Table of Contents Features ..................................................................................................... 1 1 SAM3N Description .................................................................................. 2 1.1 Configuration Summary .....................................................................................3 2 SAM3N Block Diagram ............................................................................ 4 3 Signal Description .............................
9.2 APB/AHB Bridge ..............................................................................................35 9.3 Peripheral Signal Multiplexing on I/O Lines .....................................................35 10 ARM Cortex® M3 Processor .................................................................. 39 10.1 About this section ............................................................................................39 10.2 Embedded Characteristics ......................................
SAM3N 12.3 Block Diagram ...............................................................................................209 12.4 Functional Description ...................................................................................210 12.5 Reset Controller (RSTC) User Interface ........................................................217 13 Real-time Timer (RTT) .......................................................................... 221 13.1 Description .........................................
18.2 Product Dependencies ..................................................................................275 18.3 Functional Description ...................................................................................275 18.4 Enhanced Embedded Flash Controller (EEFC) User Interface .....................286 19 Fast Flash Programming Interface (FFPI) .......................................... 291 19.1 Description ....................................................................................
SAM3N 24 Power Management Controller (PMC) ................................................ 341 24.1 Description .....................................................................................................341 24.2 Embedded Characteristics ............................................................................341 24.3 Block Diagram ...............................................................................................342 24.4 Master Clock Controller ..............................
27.8 Serial Peripheral Interface (SPI) User Interface ............................................447 28 Two-wire Interface (TWI) ..................................................................... 463 28.1 Description .....................................................................................................463 28.2 Embedded Characteristics ............................................................................464 28.3 List of Abbreviations ..........................................
SAM3N 31.4 Pin Name List ................................................................................................582 31.5 Product Dependencies ..................................................................................582 31.6 Functional Description ...................................................................................583 31.7 Timer Counter (TC) User Interface ................................................................603 32 Pulse Width Modulation Controller (PWM) ..
35.7 10-Bit DAC Characteristics ............................................................................720 35.8 AC Characteristics .........................................................................................721 36 Mechanical Characteristics ................................................................. 730 36.1 Soldering Profile ............................................................................................739 36.2 Packaging Resources ................................
Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg.
2 SAM3N 11011B–ATARM–21-Feb-12
