Datasheet

646
11011B–ATARM–21-Feb-12
SAM3N
32.7.11 PWM Channel Period Register
Name: PWM_CPRD[0..3]
Addresses: 0x40020208 [0], 0x40020228 [1], 0x40020248 [2], 0x40020268 [3]
Access: Read/Write
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
31 30 29 28 27 26 25 24
CPRD
23 22 21 20 19 18 17 16
CPRD
15 14 13 12 11 10 9 8
CPRD
76543210
CPRD
XCPRD×()
MCK
--------------------------------
CRPD DIVA×()
MCK
-------------------------------------------
CRPD DIVAB×()
MCK
-----------------------------------------------
2 XCPRD××()
MCK
-------------------------------------------
2 CPRD DIVA××()
MCK
------------------------------------------------------
2 CPRD× DIVB×()
MCK
------------------------------------------------------