Datasheet

643
11011B–ATARM–21-Feb-12
SAM3N
32.7.7 PWM Interrupt Mask Register
Name: PWM_IMR
Address: 0x40020018
Access: Read-only
• CHIDx: Channel ID.
0 = Interrupt for PWM channel x is disabled.
1 = Interrupt for PWM channel x is enabled.
32.7.8 PWM Interrupt Status Register
Name: PWM_ISR
Address: 0x4002001C
Access: Read-only
• CHIDx: Channel ID
0 = No new channel period has been achieved since the last read of the PWM_ISR register.
1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
Note: Reading PWM_ISR automatically clears CHIDx flags.
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
76543210
CHID3 CHID2 CHID1 CHID0
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
76543210
CHID3 CHID2 CHID1 CHID0