Datasheet

363
11011B–ATARM–21-Feb-12
SAM3N
24.15.9 PMC Clock Generator PLL Register
Name: CKGR_PLLR
Address: 0x400E0428
Access: Read-write
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
Warning:
Bit 29 must always be set to 1 when programming the CKGR_PLLR register.
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 374.
•DIV: Divider
• PLLCOUNT: PLL Counter
Specifies the number of Slow Clock cycles x8 before the LOCK bit is set in PMC_SR after CKGR_PLLR is written.
• MUL: PLL Multiplier
0 = The PLL is deactivated.
1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL + 1.
31 30 29 28 27 26 25 24
––1–– MUL
23 22 21 20 19 18 17 16
MUL
15 14 13 12 11 10 9 8
– – PLLCOUNT
76543210
DIV
DIV Divider Selected
0 Divider output is 0
1 Divider is bypassed (DIV = 1)
2 - 255 Divider output is DIV