Datasheet

159
11011B–ATARM–21-Feb-12
SAM3N
10.20.7.4 IPR2
10.20.7.5 IPR1
10.20.7.6 IPR0
• Priority, byte offset 3
• Priority, byte offset 2
• Priority, byte offset 1
• Priority, byte offset 0
Each priority field holds a priority value, 0-15. The lower the value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
See “The CMSIS mapping of the Cortex-M3 NVIC registers” on page 151 for more information about the IP[0] to IP[32]
interrupt priority array, that provides the software view of the interrupt priorities.
31 30 29 28 27 26 25 24
IP[11]
23 22 21 20 19 18 17 16
IP[10]
15 14 13 12 11 10 9 8
IP[9]
76543210
IP[8]
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
IP[6]
15 14 13 12 11 10 9 8
IP[5]
76543210
IP[4]
31 30 29 28 27 26 25 24
IP[3]
23 22 21 20 19 18 17 16
IP[2]
15 14 13 12 11 10 9 8
IP[1]
76543210
IP[0]