Datasheet

110
11011B–ATARM–21-Feb-12
SAM3N
10.13.3 ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with
Extend.
10.13.3.1 Syntax
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
op is one of:
ASR Arithmetic Shift Right.
LSL Logical Shift Left.
LSR Logical Shift Right.
ROR Rotate Right.
S is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see “Conditional execution” on page 84.
Rd is the destination register.
Rm is the register holding the value to be shifted.
Rs is the register holding the shift length to apply to the value in Rm. Only the least
significant byte is used and can be in the range 0 to 255.
n is the shift length. The range of shift length depends on the instruction:
ASR shift length from 1 to 32
LSL shift length from 0 to 31
LSR shift length from 1 to 32
ROR shift length from 1 to 31.
MOV{S}{cond} Rd, Rm is the preferred syntax for LSL{S}{cond} Rd, Rm, #0.
10.13.3.2 Operation
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of
places specified by constant n or register Rs.
RRX moves the bits in register Rm to the right by 1.
In all these instructions, the result is written to Rd, but the value in register Rm remains
unchanged. For details on what result is generated by the different instructions, see “Shift Oper-
ations” on page 81.
10.13.3.3 Restrictions
Do not use SP and do not use PC.
10.13.3.4 Condition flags
If S is specified:
• these instructions update the N and Z flags according to the result