Datasheet

65
11057BS–ATARM–13-Jul-12
SAM3X/A
65
11057BS–ATARM–13-Jul-12
SAM3X/A
• 128-byte transmit FIFO and 128-byte receive FIFO
• Automatic pad and CRC generation on transmitted frames
• Automatic discard of frames received with errors
• Address checking logic supports up to four specific 48-bit addresses
• Support Promiscuous Mode where all valid received frames are copied to memory
• Hash matching of unicast and multicast destination addresses
• Physical layer management through MDIO interface
• Half-duplex flow control by forcing collisions on incoming frames
• Full-duplex flow control with recognition of incoming pause frames
• Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged
•Frames
• Multiple buffers per receive and transmit frame
• Jumbo frames up to 10,240 bytes supported
12.14 True Random Number Generator (TRNG)
• Passed NIST Special Publication 800-22 Tests Suite
• Passed Diehard Random Tests Suite
• Provides a 32-bit Random Number Every 84 Clock Cycles
12.15 External Bus Interface (EBI)
• Only present on 144-pin version of SAM3X
• Managing SMC, Nand Flash accesses offering:
– Up to 8 Configurable chip select
– Programmable timing on a per chip select basis
– 16-Mbyte Address Space per Chip Select
– 8- or 16-bit Data Bus
– Word, Halfword, Byte Transfers
– Byte Write or Byte Select Lines
– Programmable Setup, Pulse and Hold Time for Read Signals per Chip Select
– Programmable Setup, Pulse and Hold Time for Write Signals per Chip Select
– Programmable Data Float Time per Chip Select
– External Wait Request
– Automatic Switch to Slow Clock Mode
– Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to
32 Bytes
– NAND Flash Controller supporting NAND Flash with Multiplexed Data/Address
buses
– Supports SLC NAND Flash technology
– Supports Hardware Error Correcting Code (ECC), 1-bit error correction, 2-bit error
detection
– Detection and Correction by Software