Datasheet

11057BS–ATARM–13-Jul-12

SAM3X/A

11057BS–ATARM–13-Jul-12

SAM3X/A

– Generation of the Wakeup signal

• Test Modes

– Remote Loopback, Local Loopback, Automatic Echo

• Interfaced with Peripheral DMA (PDC) Channels to Reduce Processor Overhead (All

USARTs) and with the DMA Controller (DMAC) (USART0 and 1)

12.5 Serial Synchronous Controller (SSC)

• Provides serial synchronous communication links used in audio and telecom applications

(with CODECs in Master or Slave Modes, I

S, TDM Buses, Magnetic Card Reader,...)

• Contains an independent receiver and transmitter and a common clock divider

• Offers a configurable frame sync and data length

• Receiver and transmitter can be programmed to start automatically or on detection of

different event on the frame sync signal

• Receiver and transmitter include a data signal, a clock signal and a frame synchronization

signal

• Interfaced with the DMA Controller (DMAC) to Reduce Processor Overhead

12.6 Timer Counter (TC)

• Three 32-bit Timer Counter Channels

• Wide range of functions including:

– Frequency Measurement

– Event Counting

– Interval Measurement

– Pulse Generation

–Delay Timing

– Pulse Width Modulation

– Up/down Capabilities

• Each channel is user-configurable and can contain:

– Three external clock inputs

– Five internal clock inputs

– Two multi-purpose input/output signals

• Two global registers that act on all three TC Channels

• Quadrature decoder

– Advanced line filtering

– Position / revolution / speed

• 2-bit Gray Up/Down Counter for Stepper Motor