Datasheet

60
11057BS–ATARM–13-Jul-12
SAM3X/A
60
11057BS–ATARM–13-Jul-12
SAM3X/A
Support for two PDC channels with connection to receiver and transmitter
Connection to Peripheral DMA Controller or DMA Controller (TWI0) Channel
Capabilities Optimizes Data Transfers
12.4 USART
Programmable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications
1, 1.5 or 2 stop bits in Asynchronous Mode, or 1 or 2 stop bits in Synchronous Mode
Parity generation and error detection
Framing error detection, overrun error detection
MSB- or LSB-first
Optional break generation and detection
By 8 or by-16 over-sampling receiver frequency
Hardware handshaking RTS-CTS
Receiver time-out and transmitter timeguard
Optional Multi-drop Mode with address generation and detection
Optional Manchester Encoding
RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
NACK handling, error counter with repetition and iteration limit
SPI Mode
–Master or Slave
Serial Clock programmable Phase and Polarity
SPI Serial Clock (SCK) Frequency up to MCK/6
IrDA modulation and demodulation
Communication at up to 115.2 Kbps
LIN Mode (USART0 only)
Compliant with LIN 1.3 and LIN 2.0 specifications
–Master or Slave
Processing of frames with up to 256 data bytes
Response Data length can be configurable or defined automatically by the Identifier
Self synchronization in Slave node configuration
Automatic processing and verification of the “Synch Break” and the “Synch Field”
The “Synch Break” is detected even if it is partially superimposed with a data byte
Automatic Identifier parity calculation/sending and verification
Parity sending and verification can be disabled
Automatic Checksum calculation/sending and verification
Checksum sending and verification can be disabled
Support both “Classic” and “Enhanced” checksum types
Full LIN error checking and reporting
Frame Slot Mode: the Master allocates slots to the scheduled frames automatically