Datasheet

59
11057BS–ATARM–13-Jul-12
SAM3X/A
59
11057BS–ATARM–13-Jul-12
SAM3X/A
12. Embedded Peripherals Overview
12.1 Serial Peripheral Interface (SPI)
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
– Four Character FIFO in Reception
• Connection to DMA Channel Capabilities Optimizes Data Transfers
– One channel for the Receiver, One Channel for the Transmitter
12.2 Two Wire Interface (TWI)
• Master, Multi-Master and Slave Mode Operation
• Compatibility with Atmel two-wire interface, serial memory and I
2
C compatible devices
• One, two or three bytes for slave address
• Sequential read/write operations
• Bit Rate: up to 400 kbit/s
• General Call Supported in Slave Mode
• SMBUS Quick Command Supported in Master Mode
• Connection to Peripheral DMA Controller (PDC) for TWI0 and TWI1 and DMA Controller
(DMAC) for TWI0 Channel Capabilities Optimizes Data Transfers in Master Mode Only
12.3 Universal Asynchronous Receiver Transceiver (UART)
•Two-pin UART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes