Datasheet

48
11057BS–ATARM–13-Jul-12
SAM3X/A
48
11057BS–ATARM–13-Jul-12
SAM3X/A
Figure 10-3. Power Management Controller Block Diagram
The SysTick calibration value is fixed at 10500, which allows the generation of a time base of
1 ms with SystTick clock to 10.5 MHz (max HCLK/8).
10.7 Watchdog Timer
• 16-bit key-protected once-only Programmable Counter
• Windowed, prevents the processor to be in a dead-lock on the watchdog access
10.8 SysTick Timer
• 24-bit down counter
• Self-reload capability
• Flexible system timer
10.9 Real Time Timer
• Real Time Timer, allowing backup of time with different accuracies
– 32-bit Free-running back-up Counter
– Integrates a 16-bit programmable prescaler running on slow clock
– Alarm Register capable to generate a wake-up of the system
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/4,...,/64
HCK
Processor
Clock
Controller
Sleep Mode
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
USB Clock Controller
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
HSCK
pck[..]
UPLL
UPLL
UOTGCK
ON/OFF
ON/OFF
FCLK
SystTick
Divider
/8
MCK