Datasheet

47
11057BS–ATARM–13-Jul-12
SAM3X/A
47
11057BS–ATARM–13-Jul-12
SAM3X/A
Figure 10-2. Clock Generator Block Diagram
10.6 Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
• the Processor Clock HCLK
• the Free running processor clock FCLK
• the Cortex SysTick external clock
• the Master Clock MCK, in particular to the Matrix and the memory interfaces
• the USB OTG HS Clock UOTGCK
• independent peripheral clocks, typically at the frequency of MCK
• three programmable clock outputs: PCK0, PCK1 and PCK2
The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The
unused oscillator is disabled automatically so that power consumption is optimized.
By default, at startup the chip runs out of the Master Clock using the Fast RC Oscillator running
at 4 MHz.
Power
Management
Controller
XIN
XOUT
Main Clock
MAINCK
UPLL Clock
UPLLCK
ControlStatus
PLL and
Divider A
PLLA Clock
PLLACK
3-20 MHz
Main
Oscillator
UPLL
On Chip
32k RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
Clock Generator
XTALSEL
HSCK
Divider
/6 /8
On Chip
12/8/4 MHz
RC OSC
MAINSEL