Datasheet

35
11057BS–ATARM–13-Jul-12
SAM3X/A
35
11057BS–ATARM–13-Jul-12
SAM3X/A
7.7 Peripheral DMA Controller
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
• Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-6. Peripheral DMA Controller
Instance Name Channel T/R 144 Pins 100 Pins
DAC Transmit X X
PWM Transmit X X
TWI1 Transmit X X
TWI0 Transmit X X
USART3 Transmit X X
USART2 Transmit X X
USART1 Transmit X X
USART0 Transmit X X
UART Transmit X X
ADC Receive X X
TWI1 Receive X X
TWI0 Receive X X
USART3 Receive X N/A
USART2 Receive X X
USART1 Receive X X
USART0 Receive X X
UART Receive X X