Datasheet

34
11057BS–ATARM–13-Jul-12
SAM3X/A
34
11057BS–ATARM–13-Jul-12
SAM3X/A
7.6 DMA Controller
• Acting as one Matrix Master
• Embeds 4 (SAM3A and 100-pin SAM3X) or 6 (144-pin SAM3X) channels
• Linked List support with Status Write Back operation at End of Transfer
• Word, HalfWord, Byte transfer support.
• Handles high speed transfer of SPI0-1, USART0-1, SSC and HSMCI (peripheral to memory,
memory to peripheral)
• Memory to memory transfer
• Can be triggered by PWM and T/C which enables to generates waveform though the
External Bus Interface
The DMA controller can handle the transfer between peripherals and memory and so receives
the triggers from the peripherals below. The hardware interface numbers are also given in Table
7-5.
Table 7-4. DMA Channels
DMA Channel Size
SAM3A
100-pin SAM3X 144-pin SAM3X
8 bytes FIFO for Channel Buffering
3
(Channels 0, 1 and 2)
4
(Channels 0, 1, 2 and 4)
32 bytes FIFO for Channel Buffering
1
(Channel 3)
2
(Channels 3 and 5)
Table 7-5. DMA Controller
Instance Name Channel T/R
DMA Channel HW
Interface Number
HSMCI Transmit/Receive 0
SPI0 Transmit 1
SPI0 Receive 2
SSC Transmit 3
SSC Receive 4
SPI1 Transmit 5
SPI1 Receive 6
TWI0 Transmit 7
TWI0 Receive 8
-- -
-- -
USART0 Transmit 11
USART0 Receive 12
USART1 Transmit 13
USART1 Receive 14
PWM Transmit 15