Datasheet

11057BS–ATARM–13-Jul-12

SAM3X/A

11057BS–ATARM–13-Jul-12

SAM3X/A

7.4 Matrix Slaves

The Bus Matrix of the SAM3X/A series product manages 9 slaves. Each slave has its own arbi-

ter, allowing a different arbitration per slave.

7.5 Master to Slave Access

All the Masters can normally access all the Slaves. However, some paths do not make sense,

for example allowing access from the USB High Speed DMA to the Internal Peripherals. Thus,

these paths are forbidden or simply not wired, and shown as “-” in the following table.

Table 7-2. List of Bus Matrix Slaves

Slave 0 Internal SRAM0

Slave 1 Internal SRAM1

Slave 2 Internal ROM

Slave 3 Internal Flash

Slave 4 USB High Speed Dual Port RAM (DPR)

Slave 5 NAND Flash Controller RAM

Slave 6 External Bus Interface

Slave 7 Low Speed Peripheral Bridge

Slave 8 High Speed Peripheral Bridge

Table 7-3. SAM3X/A Series Master to Slave Access

Masters 0 1 2 3 4 5

Slaves

Cortex-M3

I/D Bus

Cortex-M3 S

Bus PDC

USB High

Speed DMA

DMA

Controller

EMAC

DMA

0 Internal SRAM0 - X X X X X

1 Internal SRAM1 - X X X X X

2 Internal ROM X - X X X X

3 Internal Flash X - - - - -

4 USB High Speed Dual Port RAM - X - - X -

5 Nand Flash Controller RAM - X X X X X

6 External Bus Interface - X X X X X

7 Low Speed Peripheral Bridge - X X - X -

8 High Speed Peripheral Bridge - X - - X -