Features • Core • • • • • • – ARM® Cortex®-M3 revision 2.0 running at up to 84 MHz – Memory Protection Unit (MPU) – Thumb®-2 instruction set – 24-bit SysTick Counter – Nested Vector Interrupt Controller Memories – From 256 to 512 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank – From 32 to 100 Kbytes embedded SRAM with dual banks – 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines – Static Memory Controller (SMC): SRAM, NOR, NAND support.
1. SAM3X/A Description Atmel’s SAM3X/A series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 84 MHz and features up to 512 Kbytes of Flash and up to 100 Kbytes of SRAM.
SAM3X/A 1.1 Configuration Summary The SAM3X/A series devices differ in memory sizes, package and features list. Table 1-1 below summarizes the configurations. Table 1-1.
2. SAM3X/A Block Diagram UT VD D G AN ND A AN A VD DO JT AG VD DI N SE L SAM3A4/8C (100 pins) Block Diagram TD TDI O TM S TC /SW K/ D SW IO CL K Figure 2-1.
SAM3X/A VD DO UT VD DA G N ND A AN A VD DI N JT AG SE L SAM3X4/8C (100 pins) Block Diagram TD TDI O TM S TC /SW K/ D SW IO CL K Figure 2-2.
VD DO UT VD D G AN ND A AN A VD DI N JT AG SE L SAM3X4/8E (144 pins) Block Diagram TD I TD O TM S TC /SW K/ DI SW O CL K Figure 2-3.
SAM3X/A 3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripherals I/O Lines Power Supply Power 1.62V to 3.6V VDDUTMI USB UTMI+ Interface Power Supply Power 3.0V to 3.
Table 3-1.
SAM3X/A Table 3-1.
Table 3-1.
SAM3X/A Table 3-1.
Table 3-1.
SAM3X/A 4.1.1 100-lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 51 75 76 50 100 26 25 1 4.1.2 100-ball LFBGA Package Outline Figure 4-2.
4.1.3 100-lead LQFP Pinout Table 4-1.
SAM3X/A 4.1.4 Table 4-2.
4.2 SAM3X4/8E Package and Pinout The SAM3X4/8E is available in 144-lead LQFP and 144-ball LFBGA packages. 4.2.1 144-lead LQFP Package Outline Figure 4-3. Orientation of the 144-lead LQFP Package 73 108 109 72 144 37 36 1 4.2.2 144-ball LFBGA Package Outline The 144-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 10 x 10 x 1.4 mm. Figure 4-4.
SAM3X/A 4.2.3 Table 4-3.
4.2.4 144-ball LFBGA Pinout Table 4-4.
SAM3X/A 5. Power Considerations 5.1 Power Supplies The SAM3X/A series product has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V to 1.95V. • VDDIO pins: Power the Peripherals I/O lines; voltage ranges from 1.62V to 3.6V. • VDDIN pin: Powers the Voltage regulator • VDDOUT pin: It is the output of the voltage regulator.
5.3 Typical Powering Schematics The SAM3X/A series supports a 1.62V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. Figure 5-1 shows the power schematics. Figure 5-1. Single Supply VDDBU VDDUTMI VDDANA VDDIO Main Supply (1.8V-3.6V) VDDIN Voltage Regulator VDDOUT VDDCORE VDDPLL Note: 22 Restrictions For USB, VDDUTMI needs to be greater than 3.0V. For ADC, VDDANA needs to be greater than 2.0V. For DAC, VDDANA needs to be greater than 2.
SAM3X/A Figure 5-2. Core Externally Supplied VDDBU VDDUTMI VDDANA Main Supply (1.62V-3.6V) VDDIO VDDIN Voltage Regulator VDDOUT VDDCORE Supply (1.62V-1.95V) VDDCORE VDDPLL Note: Restrictions For USB, VDDUTMI needs to be greater than 3.0V. For ADC, VDDANA needs to be greater than 2.0V. For DAC, VDDANA needs to be greater than 2.4V.
Note: Backup Batteries Used FWUP SHDN Backup Batteries VDDBU VDDUTMI VDDANA VDDIO VDDIN Main Supply (1.8V-3.6V) Voltage Regulator VDDOUT VDDCORE VDDPLL Note: 1. Restrictions For USB, VDDUTMI needs to be greater than 3.0V. For ADC, VDDANA needs to be greater than 2.0V. For DAC, VDDANA needs to be greater than 2.4V. 2. VDDUTMI and VDDANA cannot be left unpowered. 5.
SAM3X/A The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz Oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off. Backup Mode is based on the Cortex-M3 deep-sleep mode with the voltage regulator disabled. The SAM3X/A series can be awakened from this mode through the Force Wake-up pin (FWUP), and Wake-up input pins WKUP0 to WKUP15, Supply Monitor, RTT or RTC wake-up event.
The processor can be awakened from an interrupt if WFI instruction of the Cortex M3 is used, or from an event if the WFE instruction is used to enter this mode. 5.5.4 Low Power Mode Summary Table The modes detailed above are the main low power modes. Each part can be set to on or off separately and wake-up sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low power modes. Table 5-1.
SAM3X/A 5.6 Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply. Figure 5-3.
5.7 Fast Start-Up The SAM3X/A series allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs. The fast restart circuitry, as shown in Figure 5-4, is fully asynchronous and provides a fast startup signal to the Power Management Controller.
SAM3X/A 6. Input/Output Lines The SAM3X/A has different kinds of input/output (I/O) lines, such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functions thanks to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in IO mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs. With a few exceptions, the I/Os have input schmitt triggers.
Table 6-1. System I/O Configuration Pin List SYSTEM_IO Bit Number Default Function After Reset Peripheral 12 Constraints for Normal Start - ERASE PC0 Low Level at startup() A TCK/SWCLK PB28 - A TDI PB29 - A TDO/TRACESWO PB30 - A TMS/SWDIO PB31 - Note: 6.2.1 Other Function Configuration In Matrix User Interface Registers (Refer to “System IO Configuration Register“ in the “Bus Matrix“ section of the product datasheet.) In PIO Controller 1.
SAM3X/A 6.4 NRST Pin The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components, or asserted low externally to reset the microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length.
7. Processor and Architecture 7.1 ARM Cortex-M3 Processor • Version 2.0 • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit. • Harvard processor architecture enabling simultaneous instruction fetch with data load/store. • Three-stage pipeline. • Single cycle 32-bit multiply. • Hardware divide. • Thumb and Debug states. • Handler and Thread modes. • Low latency ISR entry and exit. 7.
SAM3X/A 7.4 Matrix Slaves The Bus Matrix of the SAM3X/A series product manages 9 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 7-2. 7.
7.6 DMA Controller • Acting as one Matrix Master • Embeds 4 (SAM3A and 100-pin SAM3X) or 6 (144-pin SAM3X) channels Table 7-4. DMA Channels SAM3A 100-pin SAM3X 144-pin SAM3X 8 bytes FIFO for Channel Buffering 3 (Channels 0, 1 and 2) 4 (Channels 0, 1, 2 and 4) 32 bytes FIFO for Channel Buffering 1 (Channel 3) 2 (Channels 3 and 5) DMA Channel Size • Linked List support with Status Write Back operation at End of Transfer • Word, HalfWord, Byte transfer support.
SAM3X/A 7.7 Peripheral DMA Controller • Handles data transfer between peripherals and memories • Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirement The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): Table 7-6.
7.
SAM3X/A 8. Product Mapping Figure 8-1.
9. Memories 9.1 9.1.1 Embedded Memories Internal SRAM • The 100-pin SAM3A/X8 product embeds a total of 96 Kbytes high-speed SRAM (64 Kbytes SRAM0 and 32 Kbytes SRAM1). • The 100-pin SAM3A/X4 product embeds a total of 64 Kbytes high-speed SRAM (32 Kbytes SRAM0, 32 Kbytes SRAM1). • The 100-pin SAM3A/4 product embeds a total of 36 Kbytes high-speed SRAM (16 Kbytes SRAM0 and 16 Kbytes SRAM1). The SRAM0 is accessible over System Cortex-M3 bus at address 0x2000 0000 and SRAM1 at address 0x2008 0000.
SAM3X/A The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic. 9.1.3.4 Lock Regions Several lock bits used to protect write and erase operations on lock regions.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST, PA0, PA1 are set to high, PA2 and PA3 are set to low and NRST is toggled from 0 to 1. The table below shows the signal assignment of the PIO lines in FFPI mode Table 9-2. 9.1.3.
SAM3X/A The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0. 9.1.3.10 GPNVM Bits The SAM3X/A series features three GPNVM bits that can be cleared or set respectively through the “Clear GPNVM Bit” and “Set GPNVM Bit” commands of the EEFC0 User Interface. Table 9-3. General Purpose Non-volatile Memory Bits GPNVMBit[#] 9.1.
9.2 External Memories The 144-pin SAM3X features one External Memory Bus to offer interface to a wide range of external memories and to any parallel peripheral. 9.2.1 External Memory Bus • Integrates Four External Memory Controllers: – Static Memory Controller – NAND Flash Controller – SLC NAND Flash ECC Controller • Up to 24-bit Address Bus (up to 16 MBytes linear per chip select) • Up to 8 chip selects, Configurable Assignment 9.2.
SAM3X/A 10. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system such as power, resets, clocks, time, interrupts, watchdog, etc... The System Controller User Interface also embeds the registers allowing to configure the Matrix.
Figure 10-1.
SAM3X/A 10.1 System Controller and Peripherals Mapping Please refer to Figure 8-1 on page 37. All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3X/A embeds three features to monitor, warn and/or reset the chip: • Power-on-Reset on VDDBU • Brownout Detector on VDDCORE • Supply Monitor on VDDUTMI 10.2.1 Power-on-Reset on VDDBU The Power-on-Reset monitors VDDBU.
The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the Slow Clock source. The Supply Controller starts up the device by enabling the Voltage Regulator, then it generates the proper reset signals to the core power supply. It also enables to set the system in different low power modes and to wake it up from a wide range of events. 10.
SAM3X/A Figure 10-2. Clock Generator Block Diagram Clock Generator XTALSEL On Chip 32k RC OSC XIN32 XOUT32 XIN XOUT Slow Clock SLCK Slow Clock Oscillator 3-20 MHz Main Oscillator Main Clock MAINCK On Chip 12/8/4 MHz RC OSC MAINSEL UPLL HSCK Divider /6 /8 UPLL Clock UPLLCK PLL and Divider A PLLA Clock PLLACK Status Control Power Management Controller 10.6 Power Management Controller The Power Management Controller provides all the clock signals to the system.
Figure 10-3. Power Management Controller Block Diagram Processor Clock Controller HCK int Sleep Mode Divider /8 SystTick FCLK Master Clock Controller SLCK MAINCK PLLACK UPLL Prescaler /1,/2,/4,...,/64 MCK Peripherals Clock Controller periph_clk[..] ON/OFF Programmable Clock Controller MCK SLCK MAINCK PLLACK UPLL ON/OFF Prescaler /1,/2,/4,...,/64 pck[..
SAM3X/A 10.10 Real Time Clock • Low power consumption • Full asynchronous design • Two hundred year calendar • Programmable Periodic Interrupt • Alarm and update parallel load • Control of alarm and update Time/Calendar Data In 10.11 General-Purpose Backup Registers • Eight 32-bit general-purpose backup registers 10.
10.14 UART • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter 10.
SAM3X/A 11. Peripherals 11.1 Peripheral Identifiers Table 11-1 defines the Peripheral Identifiers of the SAM3X/A series. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Note that some Peripherals are always clocked. Please refer to the table below. Table 11-1.
Table 11-1.
SAM3X/A 11.2.1 PIO Controller A Multiplexing Table 11-2.
11.2.2 PIO Controller B Multiplexing Table 11-3.
SAM3X/A 11.2.3 PIO Controller C Multiplexing Table 11-4.
11.2.4 PIO Controller D Multiplexing Table 11-5.
SAM3X/A 11.2.5 PIO Controller E Multiplexing Table 11-6.
11.2.6 PIO Controller F Multiplexing Table 11-7.
SAM3X/A 12. Embedded Peripherals Overview 12.
– Support for two PDC channels with connection to receiver and transmitter – Connection to Peripheral DMA Controller or DMA Controller (TWI0) Channel Capabilities Optimizes Data Transfers 12.4 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.
SAM3X/A – Generation of the Wakeup signal • Test Modes – Remote Loopback, Local Loopback, Automatic Echo • Interfaced with Peripheral DMA (PDC) Channels to Reduce Processor Overhead (All USARTs) and with the DMA Controller (DMAC) (USART0 and 1) 12.5 Serial Synchronous Controller (SSC) • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader,...
12.
SAM3X/A – Each Slot for either a High Speed MultiMediaCard Bus (Up to 30 Cards) or an SD Memory Card • Support for Stream, Block and Multi-block Data Read and Write • Supports Connection to DMA Controller (DMAC) – Minimizes Processor Intervention for Large Buffer Transfers • Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental Access • Support for CE-ATA Completion Signal Disable Command • Protection Against Unexpected Modification On-the-Fly of the Configuration Registers
• Automatic Window Comparison of Converted Values • Write Protect Registers 12.11 Digital-to-Analog Converter (DAC) • 2 channels, 12-bit DAC • Up to 1 mega-sample conversion rate in single channel mode • Flexible conversion range • Multiple trigger sources for each channel • Built-in offset and gain calibration • Possibility to drive output to ground • Possibility to use as input to analog comparator or ADC (as an internal wire and without S/H stage) • Two PDCA channels • Power reduction mode 12.
SAM3X/A • 128-byte transmit FIFO and 128-byte receive FIFO • Automatic pad and CRC generation on transmitted frames • Automatic discard of frames received with errors • Address checking logic supports up to four specific 48-bit addresses • Support Promiscuous Mode where all valid received frames are copied to memory • Hash matching of unicast and multicast destination addresses • Physical layer management through MDIO interface • Half-duplex flow control by forcing collisions on incoming frames • Full-duple
13. Package Drawings The SAM3X/A series devices are available in QFP (LQFP or PQFP) and LFBGA packages. Figure 13-1. 100-lead LQFP Package Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
SAM3X/A Figure 13-2.
Figure 13-3.
SAM3X/A Figure 13-4.
13.1 Marking All devices are marked with the Atmel logo and the ordering code.
SAM3X/A 14. Ordering Information Table 14-1.
Revision History In the tables that follow, the most recent version of the document appears first. “rfo” indicates changes requested during the review and approval loop. Doc. Rev 11057BS Change Request Ref. Comments SDRAM Controller info removed: Section “Features”; Table 1-1, “Configuration Summary”; Table 3-1, “Signal Description List”; Section 9.2.1 “External Memory Bus”; Section 10. “System Controller”; Table 11.1, “Peripheral Identifiers”; Section 12.
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