Datasheet

32
11057BS–ATARM–13-Jul-12
SAM3X/A
32
11057BS–ATARM–13-Jul-12
SAM3X/A
7. Processor and Architecture
7.1 ARM Cortex-M3 Processor
• Version 2.0
• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit.
• Harvard processor architecture enabling simultaneous instruction fetch with data load/store.
• Three-stage pipeline.
• Single cycle 32-bit multiply.
• Hardware divide.
• Thumb and Debug states.
• Handler and Thread modes.
• Low latency ISR entry and exit.
7.2 APB/AHB Bridge
The SAM3X/A series product embeds two separate APB/AHB bridges:
• a low speed bridge
• a high speed bridge
This architecture enables a concurrent access on both bridges.
SPI, SSC and HSMCI peripherals are on the high-speed bridge connected to DMAC with the
internal FIFO for Channel buffering.
UART, ADC, TWI0-1, USART0-3, PWM, DAC and CAN peripherals are on the low-speed bridge
and have dedicated channels for the Peripheral DMA Channels (PDC). Please not that
USART0-1 can be used with the DMA as well.
The peripherals on the high speed bridge are clocked by MCK. On the low-speed bridge, CAN
controllers can be clocked at MCK divided by 2 or 4. Refer to the Power Management Controller
(PMC) section of the Full datasheet for further details.
7.3 Matrix Masters
The Bus Matrix of the SAM3X/A series product manages 5 (SAM3A) or 6 (SAM3X) masters,
which means that each master can perform an access, concurrently with others, to an available
slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all masters have the same decodings.
Table 7-1. List of Bus Matrix Masters
Master 0 Cortex-M3 Instruction/Data
Master 1 Cortex-M3 System
Master 2 Peripheral DMA Controller (PDC)
Master 3 USB OTG High Speed DMA
Master 4 DMA Controller
Master 5 Ethernet MAC (SAM3X)