Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 32 (7x7) 8-Bit 8 MHz I/O number 23

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Table Of Contents

Features
Pin Configurations
Overview
- Block Diagram
- Disclaimer
- Pin Descriptions
Resources
Data Retention
About Code Examples
Atmel AVR CPU Core
- Introduction
- Architectural Overview
- Arithmetic Logic Unit – ALU
- Status Register
- General Purpose Register File
  - The X-register, Y- register and Z-register
- Stack Pointer
- Instruction Execution Timing
- Reset and Interrupt Handling
  - Interrupt Response Time
AVR ATmega8 Memories
- In-System Reprogrammable Flash Program Memory
- SRAM Data Memory
- Data Memory Access Times
- EEPROM Data Memory
- I/O Memory
System Clock and Clock Options
- Clock Systems and their Distribution
- Clock Sources
- Crystal Oscillator
- Low-frequency Crystal Oscillator
- External RC Oscillator
- Calibrated Internal RC Oscillator
  - Oscillator Calibration Register – OSCCAL
- External Clock
- Timer/Counter Oscillator
Power Management and Sleep Modes
- MCU Control Register – MCUCR
- Idle Mode
- ADC Noise Reduction Mode
- Power-down Mode
- Power-save Mode
- Standby Mode
- Minimizing Power Consumption
System Control and Reset
- Resetting the AVR
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Control and Status Register – MCUCSR
- Internal Voltage Reference
  - Voltage Reference Enable Signals and Start-up Time
- Watchdog Timer
  - Watchdog Timer Control Register – WDTCR
- Timed Sequences for Changing the Configuration of the Watchdog Timer
  - Safety Level 1 (WDTON Fuse Unprogrammed)
  - Safety Level 2 (WDTON Fuse Programmed)
Interrupts
- Interrupt Vectors in ATmega8
  - Moving Interrupts Between Application and Boot Space
  - General Interrupt Control Register – GICR
I/O Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O Ports
External Interrupts
- MCU Control Register – MCUCR
- General Interrupt Control Register – GICR
- General Interrupt Flag Register – GIFR
8-bit Timer/Counter0
- Overview
  - Registers
  - Definitions
- Timer/Counter Clock Sources
- Counter Unit
- Operation
- Timer/Counter Timing Diagrams
- 8-bit Timer/Counter Register Description
Timer/Counter0 and Timer/Counter1 Prescalers
- Internal Clock Source
- Prescaler Reset
- External Clock Source
- Special Function IO Register – SFIOR
16-bit Timer/Counter1
- Overview
- Accessing 16-bit Registers
  - Reusing the Temporary High Byte Register
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
8-bit Timer/Counter2 with PWM and Asynchronous Operation
- Overview
  - Registers
  - Definitions
- Timer/Counter Clock Sources
- Counter Unit
- Output Compare Unit
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 8-bit Timer/Counter Register Description
- Asynchronous Operation of the Timer/Counter
- Timer/Counter Prescaler
  - Special Function IO Register – SFIOR
Serial Peripheral Interface – SPI
- SS Pin Functionality
- Data Modes
USART
- Overview
  - AVR USART vs. AVR UART – Compatibility
- Clock Generation
- Frame Formats
  - Parity Bit Calculation
- USART Initialization
- Data Transmission – The USART Transmitter
- Data Reception – The USART Receiver
- Asynchronous Data Reception
- Multi-processor Communication Mode
  - Using MPCM
- Accessing UBRRH/UCSRC Registers
  - Write Access
  - Read Access
- USART Register Description
- Examples of Baud Rate Setting
Two-wire Serial Interface
- Features
- Two-wire Serial Interface Bus Definition
  - TWI Terminology
  - Electrical Interconnection
- Data Transfer and Frame Format
- Multi-master Bus Systems, Arbitration and Synchronization
- Overview of the TWI Module
- TWI Register Description
- Using the TWI
- Transmission Modes
- Multi-master Systems and Arbitration
Analog Comparator
- Special Function IO Register – SFIOR
- Analog Comparator Control and Status Register – ACSR
- Analog Comparator Multiplexed Input
Analog-to- Digital Converter
- Features
- Starting a Conversion
- Prescaling and Conversion Timing
- Changing Channel or Reference Selection
  - ADC Input Channels
  - ADC Voltage Reference
- ADC Noise Canceler
- ADC Conversion Result
Boot Loader Support – Read- While-Write Self- Programming
- Boot Loader Features
- Application and Boot Loader Flash Sections
  - Application Section
  - BLS – Boot Loader Section
- Read-While-Write and No Read- While-Write Flash Sections
  - RWW – Read-While- Write Section
  - NRWW – No Read- While-Write Section
- Boot Loader Lock Bits
- Entering the Boot Loader Program
  - Store Program Memory Control Register – SPMCR
- Addressing the Flash During Self- Programming
- Self-Programming the Flash
Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
  - Latching of Fuses
- Signature Bytes
- Calibration Byte
- Page Size
- Parallel Programming Parameters, Pin Mapping, and Commands
  - Signal Names
- Parallel Programming
- Serial Downloading
- Serial Programming Pin Mapping
Electrical Characteristics – TA = -40°C to 85°C
- Absolute Maximum Ratings*
- DC Characteristics
- External Clock Drive Waveforms
- External Clock Drive
- Two-wire Serial Interface Characteristics
- SPI Timing Characteristics
- ADC Characteristics
Electrical Characteristics – TA = -40°C to 105°C
- Absolute Maximum Ratings*
- DC Characteristics TA = -40°C to 105°C, VCC = 2.7V to 5.5V (unless otherwise noted)
ATmega8 Typical Characteristics – TA = -40°C to 85°C
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Power-save Supply Current
- Standby Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- Bod Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
ATmega8 Typical Characteristics – TA = -40°C to 105°C
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- Bod Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
Register Summary
Instruction Set Summary
Ordering Information
Packaging Information
- 32A
- 28P3
- 32M1-A
Errata
- ATmega8 Rev. D to I, M
Datasheet Revision History
- Changes from Rev. 2486Z- 02/11 to Rev. 2486AA- 02/2013
- Changes from Rev. 2486Y- 10/10 to Rev. 2486Z- 02/11
- Changes from Rev. 2486X- 06/10 to Rev. 2486Y- 10/10
- Changes from Rev. 2486W- 02/10 to Rev. 2486X- 06/10
- Changes from Rev. 2486V- 05/09 to Rev. 2486W- 02/10
- Changes from Rev. 2486U- 08/08 to Rev. 2486V- 05/09
- Changes from Rev. 2486T- 05/08 to Rev. 2486U- 08/08
- Changes from Rev. 2486S- 08/07 to Rev. 2486T- 05/08
- Changes from Rev. 2486R- 07/07 to Rev. 2486S- 08/07
- Changes from Rev. 2486Q- 10/06 to Rev. 2486R- 07/07
- Changes from Rev. 2486P- 02/06 to Rev. 2486Q- 10/06
- Changes from Rev. 2486O-10/04 to Rev. 2486P- 02/06
- Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04
- Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04
- Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03
- Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03
- Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03
- Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03
- Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02
- Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02
- Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02
- Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02
- Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02
- Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02
- Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02
Table of Contents

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2486AA–AVR–02/2013

ATmega8(L)

Mnemonics Operands Description Operation Flags #Clocks

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC  PC + k + 1 None 1 / 2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC  PC + k + 1 None 1 / 2

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd  Rr None 1

MOVW Rd, Rr Copy Register Word

Rd+1:Rd  Rr+1:Rr

None 1

LDI Rd, K Load Immediate Rd  KNone1

LD Rd, X Load Indirect Rd  (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd  (X), X  X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X  X - 1, Rd  (X) None 2

LD Rd, Y Load Indirect Rd  (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd  (Y), Y  Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y  Y - 1, Rd  (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd  (Y + q) None 2

LD Rd, Z Load Indirect Rd  (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd  (Z), Z  Z+1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z  Z - 1, Rd  (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd  (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd  (k) None 2

ST X, Rr Store Indirect (X) Rr None 2

ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X  X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X  X - 1, (X)  Rr None 2

ST Y, Rr Store Indirect (Y)  Rr None 2

ST Y+, Rr Store Indirect and Post-Inc. (Y)  Rr, Y  Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y  Y - 1, (Y)  Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q)  Rr None 2

ST Z, Rr Store Indirect (Z)  Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z)  Rr, Z  Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z  Z - 1, (Z)  Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q)  Rr None 2

STS k, Rr Store Direct to SRAM (k)  Rr None 2

LPM Load Program Memory R0  (Z) None 3

LPM Rd, Z Load Program Memory Rd  (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Inc Rd  (Z), Z  Z+1 None 3

SPM Store Program Memory (Z)  R1:R0 None -

IN Rd, P In Port Rd  PNone1

OUT P, Rr Out Port P  Rr None 1

PUSH Rr Push Register on Stack STACK  Rr None 2

POP Rd Pop Register from Stack Rd  STACK None 2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b)  1None2

CBI P,b Clear Bit in I/O Register I/O(P,b)  0None2

LSL Rd Logical Shift Left Rd(n+1)  Rd(n), Rd(0)  0 Z, C, N, V 1

LSR Rd Logical Shift Right Rd(n)  Rd(n+1), Rd(7)  0 Z, C, N, V 1

ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z, C, N, V 1

ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z, C, N, V 1

ASR Rd Arithmetic Shift Right Rd(n)  Rd(n+1), n=0..6 Z, C, N, V 1

SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1

BSET s Flag Set SREG(s)  1 SREG(s) 1

BCLR s Flag Clear SREG(s)  0 SREG(s) 1

BST Rr, b Bit Store from Register to T T  Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b)  TNone1

SEC Set Carry C  1C1

CLC Clear Carry C  0 C 1

SEN Set Negative Flag N  1N1

CLN Clear Negative Flag N  0 N 1

SEZ Set Zero Flag Z  1Z1

CLZ Clear Zero Flag Z  0 Z 1

SEI Global Interrupt Enable I  1I1

CLI Global Interrupt Disable I 0 I 1

SES Set Signed Test Flag S  1S1

CLS Clear Signed Test Flag S  0 S 1

SEV Set Twos Complement Overflow. V  1V1

CLV Clear Twos Complement Overflow V  0 V 1

SET Set T in SREG T  1T1

Instruction Set Summary (Continued)