Datasheet
Table Of Contents
- Features
- Pin Configurations
- Overview
- Resources
- Data Retention
- About Code Examples
- Atmel AVR CPU Core
- AVR ATmega8 Memories
- System Clock and Clock Options
- Power Management and Sleep Modes
- System Control and Reset
- Interrupts
- I/O Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O Ports
- The Port B Data Register – PORTB
- The Port B Data Direction Register – DDRB
- The Port B Input Pins Address – PINB
- The Port C Data Register – PORTC
- The Port C Data Direction Register – DDRC
- The Port C Input Pins Address – PINC
- The Port D Data Register – PORTD
- The Port D Data Direction Register – DDRD
- The Port D Input Pins Address – PIND
- External Interrupts
- 8-bit Timer/Counter0
- Timer/Counter0 and Timer/Counter1 Prescalers
- 16-bit Timer/Counter1
- Overview
- Accessing 16-bit Registers
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
- Timer/Counter 1 Control Register A – TCCR1A
- Timer/Counter 1 Control Register B – TCCR1B
- Timer/Counter 1 – TCNT1H and TCNT1L
- Output Compare Register 1 A – OCR1AH and OCR1AL
- Output Compare Register 1 B – OCR1BH and OCR1BL
- Input Capture Register 1 – ICR1H and ICR1L
- Timer/Counter Interrupt Mask Register – TIMSK(1)
- Timer/Counter Interrupt Flag Register – TIFR(1)
- 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- Serial Peripheral Interface – SPI
- USART
- Two-wire Serial Interface
- Analog Comparator
- Analog-to- Digital Converter
- Boot Loader Support – Read- While-Write Self- Programming
- Boot Loader Features
- Application and Boot Loader Flash Sections
- Read-While-Write and No Read- While-Write Flash Sections
- Boot Loader Lock Bits
- Entering the Boot Loader Program
- Addressing the Flash During Self- Programming
- Self-Programming the Flash
- Performing Page Erase by SPM
- Filling the Temporary Buffer (Page Loading)
- Performing a Page Write
- Using the SPM Interrupt
- Consideration While Updating BLS
- Prevent Reading the RWW Section During Self-Programming
- Setting the Boot Loader Lock Bits by SPM
- EEPROM Write Prevents Writing to SPMCR
- Reading the Fuse and Lock Bits from Software
- Preventing Flash Corruption
- Programming Time for Flash when using SPM
- Simple Assembly Code Example for a Boot Loader
- ATmega8 Boot Loader Parameters
- Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
- Signature Bytes
- Calibration Byte
- Page Size
- Parallel Programming Parameters, Pin Mapping, and Commands
- Parallel Programming
- Enter Programming Mode
- Considerations for Efficient Programming
- Chip Erase
- Programming the Flash
- Programming the EEPROM
- Reading the Flash
- Reading the EEPROM
- Programming the Fuse Low Bits
- Programming the Fuse High Bits
- Programming the Lock Bits
- Reading the Fuse and Lock Bits
- Reading the Signature Bytes
- Reading the Calibration Byte
- Parallel Programming Characteristics
- Serial Downloading
- Serial Programming Pin Mapping
- Electrical Characteristics – TA = -40°C to 85°C
- Electrical Characteristics – TA = -40°C to 105°C
- ATmega8 Typical Characteristics – TA = -40°C to 85°C
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Power-save Supply Current
- Standby Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- Bod Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
- ATmega8 Typical Characteristics – TA = -40°C to 105°C
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata
- Datasheet Revision History
- Changes from Rev. 2486Z- 02/11 to Rev. 2486AA- 02/2013
- Changes from Rev. 2486Y- 10/10 to Rev. 2486Z- 02/11
- Changes from Rev. 2486X- 06/10 to Rev. 2486Y- 10/10
- Changes from Rev. 2486W- 02/10 to Rev. 2486X- 06/10
- Changes from Rev. 2486V- 05/09 to Rev. 2486W- 02/10
- Changes from Rev. 2486U- 08/08 to Rev. 2486V- 05/09
- Changes from Rev. 2486T- 05/08 to Rev. 2486U- 08/08
- Changes from Rev. 2486S- 08/07 to Rev. 2486T- 05/08
- Changes from Rev. 2486R- 07/07 to Rev. 2486S- 08/07
- Changes from Rev. 2486Q- 10/06 to Rev. 2486R- 07/07
- Changes from Rev. 2486P- 02/06 to Rev. 2486Q- 10/06
- Changes from Rev. 2486O-10/04 to Rev. 2486P- 02/06
- Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04
- Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04
- Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03
- Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03
- Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03
- Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03
- Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02
- Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02
- Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02
- Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02
- Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02
- Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02
- Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02
- Table of Contents
238
2486AA–AVR–02/2013
ATmega8(L)
Two-wire Serial Interface Characteristics
Table 101 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8 Two-wire Serial
Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 115 on page 239.
Notes: 1. In ATmega8, this parameter is characterized and not 100% tested
2. Required only for f
SCL
> 100kHz
3. C
b
= capacitance of one bus line in pF
4. f
CK
= CPU clock frequency
Table 101. Two-wire Serial Bus Requirements
Symbol Parameter
Condition Min Max Units
V
IL
Input Low-voltage -0.5 0.3V
CC
V
V
IH
Input High-voltage 0.7V
CC
V
CC
+ 0.5
V
hys
(1)
Hysteresis of Schmitt Trigger Inputs 0.05V
CC
(2)
–
V
OL
(1)
Output Low-voltage 3mA sink Current 0 0.4
t
r
(1)
Rise Time for both SDA and SCL 20 + 0.1C
b
(3)(2)
300
nst
of
(1)
Output Fall Time from V
IHmin
to V
ILmax
10pF < C
b
< 400pF
(3)
20 + 0.1C
b
(3)(2)
250
t
SP
(1)
Spikes Suppressed by Input Filter 0 50
(2)
I
i
Input Current each I/O Pin 0.1V
CC
< V
i
< 0.9V
CC
-10 10 µA
C
i
(1)
Capacitance for each I/O Pin – 10 pF
f
SCL
SCL Clock Frequency f
CK
(4)
> max(16f
SCL
, 250kHz)
(5)
0 400 kHz
Rp Value of Pull-up resistor
f
SCL
100kHz
f
SCL
> 100kHz
t
HD;STA
Hold Time (repeated) START Condition
f
SCL
100kHz 4.0 –
µs
f
SCL
> 100kHz 0.6 –
t
LOW
Low Period of the SCL Clock
f
SCL
100kHz
(6)
4.7 –
f
SCL
> 100kHz
(7)
1.3 –
t
HIGH
High period of the SCL clock
f
SCL
100kHz 4.0 –
f
SCL
> 100kHz 0.6 –
t
SU;STA
Set-up time for a repeated START condition
f
SCL
100kHz 4.7 –
f
SCL
> 100kHz 0.6 –
t
HD;DAT
Data hold time
f
SCL
100kHz 0 3.45
f
SCL
> 100kHz 0 0.9
t
SU;DAT
Data setup time
f
SCL
100kHz 250 –
ns
f
SCL
> 100kHz 100 –
t
SU;STO
Setup time for STOP condition
f
SCL
100kHz 4.0 –
µs
f
SCL
> 100kHz 0.6 –
t
BUF
Bus free time between a STOP and START
condition
f
SCL
100kHz 4.7 –
f
SCL
> 100kHz 1.3 –
V
CC
0.4V–
3mA
----------------------------
1000ns
C
b
-------------------
V
CC
0.4V–
3mA
----------------------------
300ns
C
b
----------------