Datasheet

19
2486AA–AVR–02/2013
ATmega8(L)
Data Memory
Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU
cycles as described in Figure 9.
Figure 9. On-chip Data SRAM Access Cycles
EEPROM Data
Memory
The ATmega8 contains 512bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
below, specifying the EEPROM Address Registers, the EEPROM Data Register, and the
EEPROM Control Register.
“Memory Programming” on page 215 contains a detailed description on EEPROM Programming
in SPI- or Parallel Programming mode.
EEPROM Read/Write
Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 1 on page 21. A self-timing function,
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V
CC
is likely to rise or fall slowly on Power-up/down. This causes the device for
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See “Preventing EEPROM Corruption” on page 23. for details on how to avoid problems in
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to “The EEPROM Control Register – EECR” on page 20 for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
clk
WR
RD
Data
Data
Address
Address Valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Vccess Instruction
Next Instruction