Datasheet
Table Of Contents
- Features
- Pin Configurations
- Overview
- Resources
- Data Retention
- About Code Examples
- Atmel AVR CPU Core
- AVR ATmega8 Memories
- System Clock and Clock Options
- Power Management and Sleep Modes
- System Control and Reset
- Interrupts
- I/O Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O Ports
- The Port B Data Register – PORTB
- The Port B Data Direction Register – DDRB
- The Port B Input Pins Address – PINB
- The Port C Data Register – PORTC
- The Port C Data Direction Register – DDRC
- The Port C Input Pins Address – PINC
- The Port D Data Register – PORTD
- The Port D Data Direction Register – DDRD
- The Port D Input Pins Address – PIND
- External Interrupts
- 8-bit Timer/Counter0
- Timer/Counter0 and Timer/Counter1 Prescalers
- 16-bit Timer/Counter1
- Overview
- Accessing 16-bit Registers
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
- Timer/Counter 1 Control Register A – TCCR1A
- Timer/Counter 1 Control Register B – TCCR1B
- Timer/Counter 1 – TCNT1H and TCNT1L
- Output Compare Register 1 A – OCR1AH and OCR1AL
- Output Compare Register 1 B – OCR1BH and OCR1BL
- Input Capture Register 1 – ICR1H and ICR1L
- Timer/Counter Interrupt Mask Register – TIMSK(1)
- Timer/Counter Interrupt Flag Register – TIFR(1)
- 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- Serial Peripheral Interface – SPI
- USART
- Two-wire Serial Interface
- Analog Comparator
- Analog-to- Digital Converter
- Boot Loader Support – Read- While-Write Self- Programming
- Boot Loader Features
- Application and Boot Loader Flash Sections
- Read-While-Write and No Read- While-Write Flash Sections
- Boot Loader Lock Bits
- Entering the Boot Loader Program
- Addressing the Flash During Self- Programming
- Self-Programming the Flash
- Performing Page Erase by SPM
- Filling the Temporary Buffer (Page Loading)
- Performing a Page Write
- Using the SPM Interrupt
- Consideration While Updating BLS
- Prevent Reading the RWW Section During Self-Programming
- Setting the Boot Loader Lock Bits by SPM
- EEPROM Write Prevents Writing to SPMCR
- Reading the Fuse and Lock Bits from Software
- Preventing Flash Corruption
- Programming Time for Flash when using SPM
- Simple Assembly Code Example for a Boot Loader
- ATmega8 Boot Loader Parameters
- Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
- Signature Bytes
- Calibration Byte
- Page Size
- Parallel Programming Parameters, Pin Mapping, and Commands
- Parallel Programming
- Enter Programming Mode
- Considerations for Efficient Programming
- Chip Erase
- Programming the Flash
- Programming the EEPROM
- Reading the Flash
- Reading the EEPROM
- Programming the Fuse Low Bits
- Programming the Fuse High Bits
- Programming the Lock Bits
- Reading the Fuse and Lock Bits
- Reading the Signature Bytes
- Reading the Calibration Byte
- Parallel Programming Characteristics
- Serial Downloading
- Serial Programming Pin Mapping
- Electrical Characteristics – TA = -40°C to 85°C
- Electrical Characteristics – TA = -40°C to 105°C
- ATmega8 Typical Characteristics – TA = -40°C to 85°C
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Power-save Supply Current
- Standby Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- Bod Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
- ATmega8 Typical Characteristics – TA = -40°C to 105°C
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata
- Datasheet Revision History
- Changes from Rev. 2486Z- 02/11 to Rev. 2486AA- 02/2013
- Changes from Rev. 2486Y- 10/10 to Rev. 2486Z- 02/11
- Changes from Rev. 2486X- 06/10 to Rev. 2486Y- 10/10
- Changes from Rev. 2486W- 02/10 to Rev. 2486X- 06/10
- Changes from Rev. 2486V- 05/09 to Rev. 2486W- 02/10
- Changes from Rev. 2486U- 08/08 to Rev. 2486V- 05/09
- Changes from Rev. 2486T- 05/08 to Rev. 2486U- 08/08
- Changes from Rev. 2486S- 08/07 to Rev. 2486T- 05/08
- Changes from Rev. 2486R- 07/07 to Rev. 2486S- 08/07
- Changes from Rev. 2486Q- 10/06 to Rev. 2486R- 07/07
- Changes from Rev. 2486P- 02/06 to Rev. 2486Q- 10/06
- Changes from Rev. 2486O-10/04 to Rev. 2486P- 02/06
- Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04
- Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04
- Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03
- Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03
- Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03
- Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03
- Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02
- Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02
- Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02
- Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02
- Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02
- Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02
- Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02
- Table of Contents
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2486AA–AVR–02/2013
ATmega8(L)
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The
MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared
when using SBI or CBI instructions.
Accessing
UBRRH/UCSRC
Registers
The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some
special consideration must be taken when accessing this I/O location.
Write Access When doing a write access of this I/O location, the high bit of the value written, the USART Reg-
ister Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is
zero during a write operation, the UBRRH value will be updated. If URSEL is one, the UCSRC
setting will be updated.
The following code examples show how to access the two registers.
Note: 1. See “About Code Examples” on page 8
As the code examples illustrate, write accesses of the two registers are relatively unaffected of
the sharing of I/O location.
Assembly Code Examples
(1)
...
; Set UBRRH to 2
ldi r16,0x02
out UBRRH,r16
...
; Set the USBS and the UCSZ1 bit to one, and
; the remaining bits to zero.
ldi r16,(1<<URSEL)|(1<<USBS)|(1<<UCSZ1)
out UCSRC,r16
...
C Code Examples
(1)
...
/* Set UBRRH to 2 */
UBRRH = 0x02;
...
/* Set the USBS and the UCSZ1 bit to one, and */
/* the remaining bits to zero. */
UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1);
...