Datasheet
Table Of Contents
- Features
- Pin Configurations
- Overview
- Resources
- Data Retention
- About Code Examples
- Atmel AVR CPU Core
- AVR ATmega8 Memories
- System Clock and Clock Options
- Power Management and Sleep Modes
- System Control and Reset
- Interrupts
- I/O Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O Ports
- The Port B Data Register – PORTB
- The Port B Data Direction Register – DDRB
- The Port B Input Pins Address – PINB
- The Port C Data Register – PORTC
- The Port C Data Direction Register – DDRC
- The Port C Input Pins Address – PINC
- The Port D Data Register – PORTD
- The Port D Data Direction Register – DDRD
- The Port D Input Pins Address – PIND
- External Interrupts
- 8-bit Timer/Counter0
- Timer/Counter0 and Timer/Counter1 Prescalers
- 16-bit Timer/Counter1
- Overview
- Accessing 16-bit Registers
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
- Timer/Counter 1 Control Register A – TCCR1A
- Timer/Counter 1 Control Register B – TCCR1B
- Timer/Counter 1 – TCNT1H and TCNT1L
- Output Compare Register 1 A – OCR1AH and OCR1AL
- Output Compare Register 1 B – OCR1BH and OCR1BL
- Input Capture Register 1 – ICR1H and ICR1L
- Timer/Counter Interrupt Mask Register – TIMSK(1)
- Timer/Counter Interrupt Flag Register – TIFR(1)
- 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- Serial Peripheral Interface – SPI
- USART
- Two-wire Serial Interface
- Analog Comparator
- Analog-to- Digital Converter
- Boot Loader Support – Read- While-Write Self- Programming
- Boot Loader Features
- Application and Boot Loader Flash Sections
- Read-While-Write and No Read- While-Write Flash Sections
- Boot Loader Lock Bits
- Entering the Boot Loader Program
- Addressing the Flash During Self- Programming
- Self-Programming the Flash
- Performing Page Erase by SPM
- Filling the Temporary Buffer (Page Loading)
- Performing a Page Write
- Using the SPM Interrupt
- Consideration While Updating BLS
- Prevent Reading the RWW Section During Self-Programming
- Setting the Boot Loader Lock Bits by SPM
- EEPROM Write Prevents Writing to SPMCR
- Reading the Fuse and Lock Bits from Software
- Preventing Flash Corruption
- Programming Time for Flash when using SPM
- Simple Assembly Code Example for a Boot Loader
- ATmega8 Boot Loader Parameters
- Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
- Signature Bytes
- Calibration Byte
- Page Size
- Parallel Programming Parameters, Pin Mapping, and Commands
- Parallel Programming
- Enter Programming Mode
- Considerations for Efficient Programming
- Chip Erase
- Programming the Flash
- Programming the EEPROM
- Reading the Flash
- Reading the EEPROM
- Programming the Fuse Low Bits
- Programming the Fuse High Bits
- Programming the Lock Bits
- Reading the Fuse and Lock Bits
- Reading the Signature Bytes
- Reading the Calibration Byte
- Parallel Programming Characteristics
- Serial Downloading
- Serial Programming Pin Mapping
- Electrical Characteristics – TA = -40°C to 85°C
- Electrical Characteristics – TA = -40°C to 105°C
- ATmega8 Typical Characteristics – TA = -40°C to 85°C
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Power-save Supply Current
- Standby Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- Bod Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
- ATmega8 Typical Characteristics – TA = -40°C to 105°C
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata
- Datasheet Revision History
- Changes from Rev. 2486Z- 02/11 to Rev. 2486AA- 02/2013
- Changes from Rev. 2486Y- 10/10 to Rev. 2486Z- 02/11
- Changes from Rev. 2486X- 06/10 to Rev. 2486Y- 10/10
- Changes from Rev. 2486W- 02/10 to Rev. 2486X- 06/10
- Changes from Rev. 2486V- 05/09 to Rev. 2486W- 02/10
- Changes from Rev. 2486U- 08/08 to Rev. 2486V- 05/09
- Changes from Rev. 2486T- 05/08 to Rev. 2486U- 08/08
- Changes from Rev. 2486S- 08/07 to Rev. 2486T- 05/08
- Changes from Rev. 2486R- 07/07 to Rev. 2486S- 08/07
- Changes from Rev. 2486Q- 10/06 to Rev. 2486R- 07/07
- Changes from Rev. 2486P- 02/06 to Rev. 2486Q- 10/06
- Changes from Rev. 2486O-10/04 to Rev. 2486P- 02/06
- Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04
- Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04
- Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03
- Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03
- Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03
- Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03
- Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02
- Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02
- Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02
- Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02
- Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02
- Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02
- Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02
- Table of Contents

118
2486AA–AVR–02/2013
ATmega8(L)
write a new value before the contents of the temporary register have been transferred to its
destination. Each of the three mentioned registers have their individual temporary register,
which means that, for example, writing to TCNT2 does not disturb an OCR2 write in
progress. To detect that a transfer to the destination register has taken place, the
Asynchronous Status Register – ASSR has been implemented
• When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the user
must wait until the written register has been updated if Timer/Counter2 is used to wake up
the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This
is particularly important if the Output Compare2 interrupt is used to wake up the device,
since the Output Compare function is disabled during writing to OCR2 or TCNT2. If the write
cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to
zero, the device will never receive a Compare Match interrupt, and the MCU will not wake up
• If Timer/Counter2 is used to wake the device up from Power-save mode, precautions must
be taken if the user wants to re-enter one of these modes: The interrupt logic needs one
TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less
than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the
user is in doubt whether the time before re-entering Power-save or Extended Standby mode
is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has
elapsed:
1. Write a value to TCCR2, TCNT2, or OCR2
2. Wait until the corresponding Update Busy Flag in ASSR returns to zero
3. Enter Power-save or Extended Standby mode
• When the asynchronous operation is selected, the 32.768kHZ Oscillator for Timer/Counter2
is always running, except in Power-down and Standby modes. After a Power-up Reset or
Wake-up from Power-down or Standby mode, the user should be aware of the fact that this
Oscillator might take as long as one second to stabilize. The user is advised to wait for at
least one second before using Timer/Counter2 after Power-up or Wake-up from Power-down
or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost
after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-
up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin
• Description of wake up from Power-save or Extended Standby mode when the timer is
clocked asynchronously: When the interrupt condition is met, the wake up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at least one
before the processor can read the counter value. After wake-up, the MCU is halted for four
cycles, it executes the interrupt routine, and resumes execution from the instruction
following SLEEP
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an
incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2
must be done through a register synchronized to the internal I/O clock domain.
Synchronization takes place for every rising TOSC1 edge. When waking up from Power-
save mode, and the I/O clock (clk
I/O
) again becomes active, TCNT2 will read as the previous
value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC
clock after waking up from Power-save mode is essentially unpredictable, as it depends on
the wake-up time. The recommended procedure for reading TCNT2 is thus as follows:
1. Write any value to either of the registers OCR2 or TCCR2
2. Wait for the corresponding Update Busy Flag to be cleared
3. Read TCNT2