Datasheet

70
ATmega8A [DATASHEET]
8159E–AVR–02/2013
15.7.4 TIFR – Timer/Counter Interrupt Flag Register
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when execut-
ing the corresponding interrupt Handling Vector. Alternatively, TOV0 is cleared by writing a logic one to the flag.
When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the
Timer/Counter0 Overflow interrupt is executed.
Bit 76543210
OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000