Datasheet

66
ATmega8A [DATASHEET]
8159E–AVR–02/2013
15. 8-bit Timer/Counter0
15.1 Features
• Single Channel Counter
• Frequency Generator
• External Event Counter
• 10-bit Clock Prescaler
15.2 Overview
Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block diagram of
the 8-bit Timer/Counter is shown in Figure 15-1. For the actual placement of I/O pins, refer to “Pin Configurations”
on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O
Register and bit locations are listed in the “Register Description” on page 69.
Figure 15-1. 8-bit Timer/Counter Block Diagram
15.2.1 Registers
The Timer/Counter (TCNT0) is an 8-bit register. Interrupt request (abbreviated to Int. Req. in the figure) signals are
all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt
Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other
timer units.
The Timer/Counter can be clocked internally or via the prescaler, or by an external clock source on the T0 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment its value. The
Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as
the timer clock (clk
T0
).
15.2.2 Definitions
Many register and bit references in this document are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 0. However, when using the register or bit defines in a program, the precise
form must be used i.e. TCNT0 for accessing Timer/Counter0 counter value and so on.
Timer/Counter
DATA BUS
TCNTn
Control Logic
= 0xFF
count
TOVn
(Int.Req.)
TCCRn
Clock Select
Tn
Edge
Detector
( From Prescaler )
clk
Tn