Datasheet

37
ATmega8A [DATASHEET]
8159E–AVR–02/2013
Figure 11-1. Reset Logic
11.2.1 Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table
26-3 on page 228. The POR is activated whenever V
CC
is below the detection level. The POR circuit can be used
to trigger the Start-up Reset, as well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset
threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V
CC
rise.
The RESET signal is activated again, without any delay, when V
CC
decreases below the detection level.
Figure 11-2. MCU Start-up, RESET
Tied to V
CC
MCU Control and Status
Register (MCUCSR)
Brown-Out
Reset Circuit
BODEN
BODLEVEL
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BUS
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
Watchdog
Oscillator
SUT[1:0]
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC