Datasheet

191
ATmega8A [DATASHEET]
8159E–AVR–02/2013
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to
ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC
Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see
“ADCL and ADCH – The ADC Data Register” on page 193.
• Bits 3:0 – MUX3:0: Analog Channel Selection Bits
The value of these bits selects which analog inputs are connected to the ADC. See Table 23-3 for details.
If these
bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in
ADCSRA is set).
23.8.2 ADCSRA – ADC Control and Status Register A
Table 23-2. Voltage Reference Selections for ADC
REFS1 REFS0 Voltage Reference Selection
0 0 AREF, Internal V
ref
turned off
01
AV
CC
with external capacitor at AREF pin
10Reserved
1 1 Internal 2.56V Voltage Reference with external capacitor at AREF pin
Table 23-3. Input Channel Selections
MUX3:0 Single Ended Input
0000 ADC0
0001 ADC1
0010 ADC2
0011 ADC3
0100 ADC4
0101 ADC5
0110 ADC6
0111 ADC7
1000
1001
1010
1011
1100
1101
1110 1.30V (V
BG
)
1111 0V (GND)
Bit 76543210
ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000