Datasheet

16
ATmega8A [DATASHEET]
8159E–AVR–02/2013
8.3 SRAM Data Memory
Figure 8-2 shows how the Atmel
®
AVR
®
ATmega8A SRAM Memory is organized.
The lower 1120 Data memory locations address the Register File, the I/O Memory, and the internal data SRAM.
The first 96 locations address the Register File and I/O Memory, and the next 1024 locations address the internal
data SRAM.
The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indi-
rect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the
indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-
register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address
registers X, Y and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM in the
ATmega8A are all accessible through all these addressing modes. The Register File is described in “General Pur-
pose Register File” on page 9.
Figure 8-2. Data Memory Map
8.3.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clk
CPU
cycles as described in Figure 8-3.
Register File
R0
R1
R2
R29
R30
R31
I/O Registers
$00
$01
$02
...
$3D
$3E
$3F
...
$0000
$0001
$0002
$001D
$001E
$001F
$0020
$0021
$0022
...
$005D
$005E
$005F
...
Data Address Space
$0060
$0061
$045E
$045F
...
Internal SRAM