Datasheet

129
ATmega8A [DATASHEET]
8159E–AVR–02/2013
by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maxi-
mum external XCK clock frequency is limited by the following equation:
Note that f
osc
depends on the stability of the system clock source. It is therefore recommended to add some margin
to avoid possible loss of data due to frequency variations.
20.3.4 Synchronous Clock Operation
When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock out-
put (Master). The dependency between the clock edges and data sampling or data change is the same. The basic
principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is
changed.
Figure 20-3. Synchronous Mode XCK Timing
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data
change. As Figure 20-3 shows, when UCPOL is zero the data will be changed at rising XCK edge and sampled at
falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge.
20.4 Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and option-
ally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of
nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits,
before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the com-
munication line can be set to an idle (high) state. Figure 20-4 illustrates the possible combinations of the frame
formats. Bits inside brackets are optional.
f
XCK
f
OSC
4
-----------

RxD / TxD
XCK
RxD / TxD
XCK
UCPOL = 0
UCPOL = 1
Sample
Sample