Datasheet

113
ATmega8A [DATASHEET]
8159E–AVR–02/2013
Table 18-4 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode.
Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but
the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 105 for more details.
Table 18-5 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode.
Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but
the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 106 for more details.
• Bit 2:0 – CS22:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Table 18-6.
18.11.2 TCNT2 – Timer/Counter Register
Table 18-4. Compare Output Mode, Fast PWM Mode
(1)
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
01Reserved
1 0 Clear OC2 on Compare Match, set OC2 at BOTTOM,
(non-inverting mode)
1 1 Set OC2 on Compare Match, clear OC2 at BOTTOM,
(inverting mode)
Table 18-5. Compare Output Mode, Phase Correct PWM Mode
(1)
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
01Reserved
10
Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match
when downcounting.
11
Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match
when downcounting.
Table 18-6. Clock Select Bit Description
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/Counter stopped).
001clk
T2S
/(No prescaling)
010clk
T2S
/8 (From prescaler)
011clk
T2S
/32 (From prescaler)
100clk
T2S
/64 (From prescaler)
101clk
T2S
/128 (From prescaler)
110clk
T
2
S
/256 (From prescaler)
111clk
T
2
S
/1024 (From prescaler)
Bit 76543210
TCNT2[7:0] TCNT2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000