8-bit Atmel Microcontroller with 8KB In-System Programmable Flash ATmega8A Features • High-performance, Low-power Atmel®AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 130 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16MIPS Throughput at 16MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 8KBytes of In-System Self-programmable Flash program memory – 512Bytes EE
1.
2. Overview The Atmel®AVR® ATmega8A is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8A achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1.
The Atmel®AVR® AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 56 and “System Clock and Clock Options” on page 24. 2.2.4 Port C (PC5:PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated.
3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device.
. AVR CPU Core Overview This section discusses the Atmel®AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format.
• Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.
Figure 7-2. AVR CPU General Purpose Working Registers 7 0 Addr.
locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled.
Figure 7-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7-5.
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software.
7.7.1 Interrupt Response Time The interrupt execution response for all the enabled Atmel®AVR® interrupts is four clock cycles minimum. After four clock cycles, the Program Vector address for the actual interrupt handling routine is executed. During this 4-clock cycle period, the Program Counter is pushed onto the Stack. The Vector is normally a jump to the interrupt routine, and this jump takes three clock cycles.
8. AVR Memories 8.1 Overview This section describes the different memories in the Atmel®AVR® ATmega8A. The AVR architecture has two main memory spaces, the Data memory and the Program Memory space. In addition, the ATmega8A features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 8.2 In-System Reprogrammable Flash Program Memory The ATmega8A contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage.
8.3 SRAM Data Memory Figure 8-2 shows how the Atmel®AVR®ATmega8A SRAM Memory is organized. The lower 1120 Data memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 1024 locations address the internal data SRAM. The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment.
Figure 8-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address Valid Write Data WR Read Data RD Memory Vccess Instruction 8.4 Next Instruction EEPROM Data Memory The Atmel®AVR®ATmega8A contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
The calibrated Oscillator is used to time the EEPROM accesses. Table 8-4 lists the typical programming time for EEPROM access from the CPU. Figure 8-4. EEPROM Programming Time Symbol EEPROM Write (from CPU) Note: Number of Calibrated RC Oscillator Cycles(1) Typ Programming Time 8448 8.5ms 1. Uses 1MHz clock, independent of CKSEL Fuse settings.
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
needed detection level, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
9. System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 32. The clock systems are detailed Figure 9-1. Figure 9-1.
9.1.3 Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 9.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode.
When CKOPT is unprogrammed, the Oscillator has a smaller output swing. This reduces power consumption considerably. This mode has a limited frequency range and it cannot be used to drive other clock buffers. For resonators, the maximum frequency is 8MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators.
Table 9-4. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1:0 Start-up Time from Power-down and Power-save 0 00 258 CK(1) 4.1 ms Ceramic resonator, fast rising power 0 01 258 CK(1) 65 ms Ceramic resonator, slowly rising power 0 10 1K CK(2) – Ceramic resonator, BOD enabled 0 11 1K CK(2) 4.1 ms Ceramic resonator, fast rising power 1 00 1K CK(2) 65 ms Ceramic resonator, slowly rising power 1 01 16K CK – 1 10 16K CK 4.
Figure 9-3. External RC Configuration VCC NC R XTAL2 XTAL1 C GND The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3:0 as shown in Table 9-6. Table 9-6. External RC Oscillator Operating Modes CKSEL3:0 Frequency Range (MHz) 0101 0.1 - 0.9 0110 0.9 - 3.0 0111 3.0 - 8.0 1000 8.0 - 12.0 When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 9-7.
9.6 Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0MHz clock. All frequencies are nominal values at 5V and 25C. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 9-8. If selected, it will operate with no external components. The CKOPT Fuse should always be unprogrammed when using this clock option.
9.7 External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 9-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND, and XTAL2 and GND. Figure 9-4. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 9-10.
9.9 9.9.1 Register Description OSCCAL – Oscillator Calibration Register Bit Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value Writing the calibration byte to this address will trim the Internal Oscillator to remove process variations from the Oscillator frequency.
10. Power Management and Sleep Modes 10.1 Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. Figure 9-1 on page 24 presents the different clock systems in the ATmega8A, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 10-1 shows the different clock options and their wake-up sources.
the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR.
10.6 Standby Mode When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in 6 clock cycles. 10.7 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system.
details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power. 10.8 Register Description 10.8.1 MCUCR – MCU Control Register The MCU Control Register contains control bits for power management.
11. System Control and Reset 11.1 Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the boot section or vice versa.
Figure 11-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Control and Status Register (MCUCSR) Brown-Out Reset Circuit BODEN BODLEVEL Pull-up Resistor SPIKE FILTER Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 11.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 26-3 on page 228. The POR is activated whenever VCC is below the detection level.
Figure 11-3. MCU Start-up, RESET Extended Externally VCC VPOT RESET TIME-OUT VRST tTOUT INTERNAL RESET 11.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 26-3 on page 228) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Figure 11-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNAL RESET 11.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period tTOUT. Refer to page 40 for details on operation of the Watchdog Timer. Figure 11-6. Watchdog Reset During Operation CC CK 11.3 Internal Voltage Reference ATmega8A features an internal bandgap reference.
11.4 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 11-7 on page 40. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
WDT_off: ; reset WDT WDR ; Write logical one to WDCE and WDE in r16, WDTCR ori r16, (1<
11.6 Register Description 11.6.1 MCUCSR – MCU Control and Status Register The MCU Control and Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUCSR See Bit Description • Bit 7:4 – Res: Reserved Bits These bits are reserved bits in the ATmega8A and always read as zero.
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. • Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0 The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
12. Interrupts This section describes the specifics of the interrupt handling performed by the ATmega8A. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. 12.1 Interrupt Vectors in ATmega8A Table 12-1. Vector No.
Table 12-2. BOOTRST Note: Reset and Interrupt Vectors Placement (1) IVSEL Reset Address Interrupt Vectors Start Address 1 0 0x000 0x001 1 1 0x000 Boot Reset Address + 0x001 0 0 Boot Reset Address 0x001 0 1 Boot Reset Address Boot Reset Address + 0x001 1. The Boot Reset Address is shown in Table 24-6 on page 204. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code $000 ; $001 rjmp RESET:ldi Comments RESET ; Reset handler r16,high(RAMEND); Main program start $002 out SPH,r16 $003 ldi r16,low(RAMEND) ; Set Stack Pointer to top of RAM $004 out SPL,r16 $005 sei $006 ; Enable inter
When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes, and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code Comments ; .org $c00 $c00 $c01 rjmp rjmp RESET EXT_INT0 ; Reset handler ; IRQ0 Handler $c02 rjmp EXT_INT1 ; IRQ1 Handler :. :. :.
• Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
13. I/O Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
13.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a functional description of one I/O port pin, here generically called Pxn. Figure 13-2. General Digital I/O(1) PUD Q D DDxn Q CLR RESET WDx Q Pxn D PORTxn Q CLR WPx DATA BUS RDx RESET SLEEP RRx SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 13.2.
difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tristate ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step. Table 13-1 summarizes the control signals for the pin value. Table 13-1. 13.2.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 13-4.
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) :.
13.2.4 Unconnected pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
Table 13-6 summarizes the function of the overriding signals. The pin and port indexes from Figure 13-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Figure 13-6. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
• Bit 2 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 50 for more details about this feature. 13.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 13-2. Table 13-2.
• SCK – Port B, Bit 5 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit. • MISO – Port B, Bit 4 MISO: Master Data input, Slave Data output pin for SPI channel.
Table 13-3.
13.3.3 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 13-5. Table 13-5.
• ADC0 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power. Table 13-6 and Table 13-7 relate the alternate functions of Port C to the overriding signals shown in Figure 13-5 on page 54. Table 13-6.
13.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-8. Table 13-8.
Table 13-9 and Table 13-10 relate the alternate functions of Port D to the overriding signals shown in Figure 13-5 on page 54. Table 13-9. Overriding Signals for Alternate Functions PD7:PD4 Signal Name PD7/AIN1 PD6/AIN0 PD5/T1 PD4/XCK/T0 PUOE 0 0 0 0 PUO 0 0 0 0 OOE 0 0 0 0 OO 0 0 0 0 PVOE 0 0 0 UMSEL PVO 0 0 0 XCK OUTPUT DIEOE 0 0 0 0 DIEO 0 0 0 0 DI – – T1 INPUT XCK INPUT / T0 INPUT AIO AIN1 INPUT AIN0 INPUT – – Table 13-10.
13.4.3 PINB – The Port B Input Pins Address Bit 13.4.4 7 6 5 4 3 2 1 0 PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 Read/Write R R R R R R R R Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PORTC – The Port C Data Register Bit 13.4.
14. External Interrupts The external interrupts are triggered by the INT0, and INT1 pins. Observe that, if enabled, the interrupts will trigger even if the INT0:1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register – MCUCR.
longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 14-2. 14.1.2 Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request.
15. 8-bit Timer/Counter0 15.1 Features • • • • 15.2 Single Channel Counter Frequency Generator External Event Counter 10-bit Clock Prescaler Overview Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 15-1. For the actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold.
The definitions in Table 15-1 are also used extensively throughout this datasheet. Table 15-1. 15.3 Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x00 MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255) Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source.
15.6 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 15-3 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value. Figure 15-3.
15.7 15.7.1 Register Description TCCR0 – Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 – – – – – CS02 CS01 CS00 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0 • Bit 2:0 – CS02:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter. Table 15-2. CS02 Clock Select Bit Description CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped).
15.7.4 TIFR – Timer/Counter Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, TOV0 is cleared by writing a logic one to the flag.
16. Timer/Counter0 and Timer/Counter1 Prescalers 16.1 Overview Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.2 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle.
17. 16-bit Timer/Counter1 17.1 Features • • • • • • • • • • • 17.2 True 16-bit Design (i.e.
Figure 17-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int. Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCFnA (Int. Req.) Waveform Generation = OCnA DATA BUS OCRnA OCFnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 17.2.1 TCCRnB 1.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (see “Analog Comparator” on page 179). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values.
Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16-bit registers does not involve using the temporary register. To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low byte must be read before the High byte. The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Figure 17-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int. Req.) TEMP (8-bit) Clock Select count TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) clear direction Control Logic clkTn Edge Detector Tn ( From Prescaler ) TOP BOTTOM Signal description (internal signals): count Increment or decrement TCNT1 by 1. direction Select between increment and decrement. clear Clear TCNT1 (set all bits to zero). clkT1 Timer/Counter clock. TOP Signalize that TCNT1 has reached maximum value.
quency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 17-3. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. Figure 17-3.
Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 16-1 on page 71). The edge detector is also identical.
Figure 17-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 17-4. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf.
17.7.2 Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. 17.7.
The general I/O port function is overridden by the Output Compare (OC1x) from the waveform generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions.
counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 17-6. The counter value (TCNT1) increases until a Compare Match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 17-6.
mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature.
compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. Figure 17-8. Phase Correct PWM Mode, Timing Diagram OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM.
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
Figure 17-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM).
If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 17.10 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering).
Figure 17-12. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value Figure 17-13 shows the same timing data, but with the prescaler enabled. Figure 17-13.
pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting.
• Bit 3 – FOC1A: Force Output Compare for channel A • Bit 2 – FOC1B: Force Output Compare for channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate Compare Match is forced on the waveform generation unit.
17.11.2 TCCR1B – Timer/Counter 1 Control Register B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1B • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture Pin (ICP1) is filtered.
17.11.3 TCNT1H and TCNT1L – Timer/Counter 1 Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter.
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 75. 17.11.7 TIMSK(1) – Timer/Counter Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 Note: TIMSK 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. • Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation Features • • • • • • • 18.2 Single Channel Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, phase Correct Pulse Width Modulator (PWM) Frequency Generator 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV2 and OCF2) Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock Overview Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
18.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units.
Figure 18-2. Counter Unit Block Diagram TOVn (Int. Req.) DATA BUS TOSC1 count clear TCNTn Control Logic clk Tn Prescaler T/C Oscillator direction BOTTOM TOSC2 TOP clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkT2 Timer/Counter clock. TOP Signalizes that TCNT2 has reached maximum value. BOTTOM Signalizes that TCNT2 has reached minimum value (zero).
Figure 18-3. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Comparator ) OCFn (Int. Req.) TOP BOTTOM Waveform Generator OCxy FOCn WGMn1:0 COMn1:0 The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence.
missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even when changing between waveform generation modes.
The design of the Output Compare Pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 112. 18.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes.
Figure 18-5. CTC Mode, Timing Diagram OCn Interrupt Flag Set TCNTn OCn (Toggle) Period (COMn1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
Figure 18-6. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin.
has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle.
At the very start of period 2 in Figure 18-7 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match: 18.8 • OCR2A changes its value from MAX, like in Figure 18-7. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match.
Figure 18-10. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 18-11 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP OCRn BOTTOM BOTTOM + 1 TOP OCFn 18.
• The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the Oscillator frequency. • When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1.
processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare Pin is changed on the timer clock and is not synchronized to the processor clock. 18.10 Timer/Counter Prescaler Figure 18-12. Prescaler for Timer/Counter2 PSR2 clkT2S/1024 clkT2S/256 clkT2S/128 AS2 clkT2S/64 10-BIT T/C PRESCALER Clear clkT2S/32 TOSC1 clkT2S clkT2S/8 clkI/O 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S.
18.11 Register Description 18.11.1 TCCR2 – Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR2 • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode.
Table 18-4 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 18-4. Compare Output Mode, Fast PWM Mode(1) COM21 COM20 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match, set OC2 at BOTTOM, (non-inverting mode) 1 1 Set OC2 on Compare Match, clear OC2 at BOTTOM, (inverting mode) Note: Description 1. A special case occurs when OCR2 equals TOP and COM21 is set.
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register. 18.11.
18.11.5 TIMSK – Timer/Counter Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK • Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled.
19. Serial Peripheral Interface – SPI 19.1 Features • • • • • • • • Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8A and peripheral devices or between several AVR devices. Figure 19-1. SPI Block Diagram(1) DIVIDER /2/4/8/16/32/64/128 SPI2X SPI2X 19.
the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line.
Table 19-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See “Port B Pins Alternate Functions” on page 56 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
19.3 SS Pin Functionality 19.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs except MISO which can be user configured as an output, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
Figure 19-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 19-4.
19.5 19.5.1 Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the global interrupt enable bit in SREG is set. • Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled.
Table 19-5. 19.5.2 Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 SPR0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 SCK Frequency fosc/4 fosc/16 fosc/64 fosc/128 fosc/2 fosc/8 fosc/32 fosc/64 SPSR – SPI Status Register Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set.
The SPI Data Register is a Read/Write Register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. 20. USART 20.1 Features • • • • • • • • • • • • 20.
Figure 20-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL DATABUS UDR (Transmit) PARITY GENERATOR TxD Receiver CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER UCSRB RxD UCSRC 1. Refer to “Pin Configurations” on page 2, Table 13-10 on page 62, and Table 13-9 on page 62 for USART pin placement.
• Transmit Buffer Functionality. • Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer. Therefore the UDR must only be read once for each incoming data! More important is the fact that the Error Flags (FE and DOR) and the ninth data bit (RXB8) are buffered with the data in the receive buffer.
20.3.1 xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation. fosc XTAL pin frequency (System Clock). Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the Synchronous Master modes of operation. The description in this section refers to Figure 20-2. The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a programmable prescaler or baud rate generator.
by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation: f OSC f XCK ----------4 Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 20.3.
Figure 20-4. Frame Formats FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting.
assumed to be stored in the r17:r16 Registers. When the function writes to the UCSRC Register, the URSEL bit (MSB) must be set due to the sharing of I/O location by UBRRH and UCSRC.
20.6.1 Sending Frames with 5 to 8 Data Bits A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDR I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame.
20.6.2 Sending Frames with 9 Data Bits If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the Low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get and return received data from buffer in r16, UDR ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRA & (1<
The following code example shows a simple USART receive function that handles both 9-bit characters and the status bits.
20.6.9 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero.
of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost. 20.6.13 Flushing the Receive Buffer The Receiver buffer FIFO will be flushed when the Receiver is disabled (i.e., the buffer will be emptied of its contents). Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC Flag is cleared.
then uses samples 8, 9 and 10 for Normal mode, and samples 4, 5 and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recovery logic is synchronized and the data recovery can begin.
generated baud rate of the Receiver does not have a similar (see Table 20-2) base frequency, the Receiver will not be able to synchronize the frames to the start bit. The following equations can be used to calculate the ratio of the incoming data rate and internal Receiver baud rate.
The recommendations of the maximum Receiver baud rate error was made under the assumption that the Receiver and Transmitter equally divides the maximum total error. There are two possible sources for the Receivers Baud Rate error. The Receiver’s system clock (XTAL) will always have some minor instability over the supply voltage range and the temperature range.
20.9 Accessing UBRRH/UCSRC Registers The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. 20.9.1 Write Access When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated.
Assembly Code Example(1) USART_ReadUCSRC: ; Read UCSRC in r16,UBRRH in r16,UCSRC ret C Code Example(1) unsigned char USART_ReadUCSRC( void ) { unsigned char ucsrc; /* Read UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; } Note: 1. See “About Code Examples” on page 6. The assembly code example returns the UCSRC value in r16.
20.10.2 UCSRA – USART Control and Status Register A Bit 7 6 5 4 3 2 1 0 RXC TXC UDRE FE DOR PE U2X MPCM Read/Write R R/W R R R R R/W R/W Initial Value 0 0 1 0 0 0 0 0 UCSRA • Bit 7 – RXC: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e. does not contain any unread data).
20.10.3 UCSRB – USART Control and Status Register B Bit 7 6 5 4 3 2 1 0 RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 UCSRB • Bit 7 – RXCIE: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC Flag.
The UCSRC Register shares the same I/O location as the UBRRH Register. See the “Accessing UBRRH/UCSRC Registers” on page 142 section which describes how to access this register. • Bit 7 – URSEL: Register Select This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when reading UCSRC. The URSEL must be one when writing the UCSRC. • Bit 6 – UMSEL: USART Mode Select This bit selects between Asynchronous and Synchronous mode of operation. Table 20-4.
Table 20-7. UCSZ Bits Settings (Continued) UCSZ2 UCSZ1 UCSZ0 Character Size 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit • Bit 0 – UCPOL: Clock Polarity This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Table 20-8. UCPOL 20.10.
Receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see “Asynchronous Operational Range” on page 139). The error values are calculated using the following equation: BaudRate Closest Match - – 1 100% Error[%] = ------------------------------------------------------ BaudRate Table 20-9. Examples of UBRR Settings for Commonly Used Oscillator Frequencies fosc = 1.0000MHz fosc = 1.8432MHz fosc = 2.
Table 20-10. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.
Table 20-11. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000MHz fosc = 14.7456MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.
Table 20-12. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.
21. Two-wire Serial Interface 21.1 Features • • • • • • • • • • 21.
sponding to the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need for external ones. 21.2.2 Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR).
The TWINT Flag is set in the following situations: • After the TWI has transmitted a START/REPEATED START condition. • After the TWI has transmitted SLA+R/W. • After the TWI has transmitted an address byte. • After the TWI has lost arbitration. • After the TWI has been addressed by own slave address or general call. • After the TWI has received a data byte. • After a STOP or REPEATED START has been received while still addressed as a Slave.
pull-up resistors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any bus operation. The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical characteristics of the TWI is given in “Twowire Serial Interface Characteristics” on page 229.
Figure 21-4. START, REPEATED START and STOP conditions SDA SCL START 21.4.3 STOP REPEATED START START STOP Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
Figure 21-6. Data Packet Format Data MSB Data LSB ACK 8 9 Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 2 SLA+R/W 21.4.5 7 STOP, REPEATED START or Next Data Byte Data Byte Combining Address and Data Packets into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal.
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one from the Master with the shortest high period. The low period of the combined clock is equal to the low period of the Master with the longest low period.
Figure 21-9. Arbitration Between Two Masters START SDA from Master A Master A Loses Arbitration, SDAA SDA SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit. • A STOP condition and a data bit. • A REPEATED START and a STOP condition. It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
Application Action Figure 21-10. Interfacing the Application to the TWI in a Typical Transmission 1. Application writes to TWCR to initiate transmission of START TWI Hardware Action TWI bus 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, makin sure that TWINT is written to one, and TWSTA is written to zero. START 2. TWINT set. Status code indicates START condition sent SLA+W 5.
the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must write a specific value to TWCR, instructing the TWI hardware to transmit a STOP condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.
Assembly Code Example 1 ldi r16, (1<
The following sections describe each of these modes. Possible status codes are described along with figures detailing data transmission in each of the modes.
mitted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see Table 21-3). In order to enter MT mode, SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer.
Table 21-3.
Figure 21-12.
Figure 21-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER ........ Device 3 Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag.
Table 21-4.
21.6.4 Slave Receiver Mode In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter (see Figure 21-5). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Table 21-5. Data transfer in Slave Receiver mode VCC Device 1 Device 2 SLAVE RECEIVER MASTER TRANSMITTER ........
Table 21-6.
Figure 21-15. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address.
Table 21-7.
21.6.6 Miscellaneous States There are two status codes that do not correspond to a defined TWI state, see Table 21-9. Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer. Status 0x00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame.
allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a Slave Receiver. Figure 21-18. An Arbitration Example VCC Device 1 Device 2 Device 3 MASTER TRANSMITTER MASTER TRANSMITTER SLAVE RECEIVER ........
21.8 21.8.1 Register Description TWBR – TWI Bit Rate Register Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TWBR • Bits 7:0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
• Bit 4 – TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state.
21.8.4 TWDR – TWI Data Register Bit 7 6 5 4 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 TWDR In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware.
22. Analog Comparator 22.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
Table 22-1. ACME ADEN MUX2:0 1 0 001 ADC1 1 0 010 ADC2 1 0 011 ADC3 1 0 100 ADC4 1 0 101 ADC5 1 0 110 ADC6 1 0 111 ADC7 Note: 22.3 22.3.1 Analog Comparator Multiplexed Input(1) Analog Comparator Negative Input 1. ADC7:6 are only available in TQFP and QFN/MLF Package.
• Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, ACI is cleared by writing a logic one to the flag.
23. Analog-to-Digital Converter 23.1 Features • • • • • • • • • • • • • 23.2 10-bit Resolution 0.5LSB Integral Non-linearity ± 2LSB Absolute Accuracy 13 - 260µs Conversion Time Up to 15kSPS at Maximum Resolution 6 Multiplexed Single Ended Input Channels 2 Additional Multiplexed Single Ended Input Channels (TQFP and QFN/MLF Package only) Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
Figure 23-1. Analog to Digital Converter Block Schematic Operation ADC CONVERSION COMPLETE IRQ 15 ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADFR ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL. & STATUS REGISTER (ADCSRA) MUX0 MUX2 MUX1 MUX3 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS MUX DECODER CHANNEL SELECTION PRESCALER AVCC CONVERSION LOGIC INTERNAL 2.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In single conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
Table 23-1. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) Extended conversion 13.5 25 Normal conversions, single ended 1.5 13 Condition 23.5 Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion.
If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch between AVCC and 2.56V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 23.
23.6.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the ground plane, and keep them well away from high-speed switching digital tracks. 2.
Figure 23-8. Offset Error Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage • Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5LSB below maximum). Ideal value: 0LSB Figure 23-9.
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1LSB). Ideal value: 0LSB. Figure 23-11. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1LSB wide) will code to the same value. Always ±0.5LSB.
Table 23-2. Voltage Reference Selections for ADC REFS1 REFS0 Voltage Reference Selection 0 0 AREF, Internal Vref turned off 0 1 AVCC with external capacitor at AREF pin 1 0 Reserved 1 1 Internal 2.56V Voltage Reference with external capacitor at AREF pin • Bit 5 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted.
• Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. • Bit 6 – ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion.
23.8.3 ADCL and ADCH – The ADC Data Register 23.8.3.1 ADLAR = 0 Bit Read/Write Initial Value 23.8.3.
24. Boot Loader Support – Read-While-Write Self-Programming 24.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 24.2 1. A page is a section in the Flash consisting of several bytes (see Table 25-5 on page 210) used during programming.
(RWW) section and the No Read-While-Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 24-7 on page 204 and Figure 24-2 on page 196. The main difference between the two sections is: • When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation. • When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation.
Figure 24-1. Read-While-Write vs. No Read-While-Write Read-While-Write (RWW) Section Z-pointer Addresses NRWW section Z-pointer Addresses RWW section No Read-While-Write (NRWW) Section CPU is Halted during the Operation Code Located in NRWW Section Can be Read during the Operation Figure 24-2.
Note: 24.5 1. The parameters in the figure are given in Table 24-6 on page 204. Boot Loader Lock Bits If no Boot Loader capability is needed, the entire Flash is available for application code. The Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. The user can select: • To protect the entire Flash from a software update by the MCU.
24.6 Entering the Boot Loader Program Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the application code is loaded, the program can start executing the application code.
Figure 24-3. Addressing the Flash during SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PAGE ADDRESS WITHIN THE FLASH PCWORD WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Notes: 1. The different variables used in the figure are listed in Table 24-8 on page 204. 2. PCPAGE and PCWORD are listed in Table 25-5 on page 210. 24.
24.8.1 Performing Page Erase by SPM To execute page erase, set up the address in the Z-pointer, write “X0000011” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. • Page Erase to the RWW section: The NRWW section can be read during the page erase. • Page Erase to the NRWW section: The CPU is halted during the operation.
24.8.7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock Bits, write the desired data to R0, write “X0001001” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The only accessible Lock Bits are the Boot Lock Bits that may prevent the Application and Boot Loader section from any software update by the MCU.
24.8.10 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
; transfer data from RAM to Flash page buffer ldi looplo, low(PAGESIZEB) ;init loop variable ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 Wrloop: ld r0, Y+ ld r1, Y+ ldi spmcrval, (1<
; SPM timed sequence out SPMCR, spmcrval spm ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret 24.8.13 Boot Loader Parameters In Table 24-6 through Table 24-8, the parameters used in the description of the self programming are given. Table 24-6.
Note: 1. Z15:Z13: always ignored Z0: should be zero for all SPM commands, byte select for the LPM instruction. See “Addressing the Flash During Self-Programming” on page 198 for details about the use of Z-pointer during Self-Programming. 24.9 Register Description 24.9.1 Store Program Memory Control Register – SPMCR The Store Program memory Control Register contains the control bits needed to control the Boot Loader operations.
• Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Zpointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles.
25. Memory Programming 25.1 Program And Data Memory Lock Bits The ATmega8A provides six Lock Bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 25-2. The Lock Bits can only be erased to “1” with the Chip Erase command. Table 25-1.
Table 25-2. Lock Bit Protection Modes(2) (Continued) Memory Lock Bits 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
Table 25-4. Fuse Low Byte Fuse Low Byte Bit No.
25.5 Page Size Table 25-5. No. of Words in a Page and no. of Pages in the Flash Flash Size 4K words (8K bytes) Table 25-6. 25.6 Page Size PCWORD No. of Pages PCPAGE PCMSB 32 words PC[4:0] 128 PC[11:5] 11 No. of Words in a Page and no. of Pages in the EEPROM EEPROM Size Page Size PCWORD No.
Table 25-7.
Table 25-10. Command Byte Bit Coding Command Byte Command Executed 0000 0100 Read Fuse and Lock Bits 0000 0010 Read Flash 0000 0011 Read EEPROM 25.7 Parallel Programming 25.7.1 Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5 - 5.5V between VCC and GND, and wait at least 100µs. 2. Set RESET to “0” and toggle XTAL1 at least 6 times 3. Set the Prog_enable pins listed in Table 25-8 on page 211 to “0000” and wait at least 100 ns. 4. Apply 11.
1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. 25.7.4 Programming the Flash The Flash is organized in pages, see Table 25-5 on page 210. When programming the Flash, the program data is latched into a page buffer.
H. Program Page 1. Set BS1 = “0” 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 3. Wait until RDY/BSY goes high. (See Figure 25-12 for signal waveforms) I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse.
Table 25-12. Programming the Flash Waveforms(1) F A DATA 0x10 B ADDR. LOW C DATA LOW D E B C D E DATA HIGH XX ADDR. LOW DATA LOW DATA HIGH XX G H ADDR. HIGH XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: 25.7.5 1. “XX” is don’t care. The letters refer to the programming description above. Programming the EEPROM The EEPROM is organized in pages, see Table 25-6 on page 210. When programming the EEPROM, the program data is latched into a page buffer.
Figure 25-2. Programming the EEPROM Waveforms K A DATA 0x11 G ADDR. HIGH B C ADDR. LOW DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 25.7.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 213 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. G: Load Address High byte (0x00 - 0xFF). 3. B: Load Address Low byte (0x00 - 0xFF). 4.
4. Give WR a negative pulse and wait for RDY/BSY to go high. 25.7.9 Programming the Fuse High Bits The algorithm for programming the Fuse high bits is as follows (refer to “Programming the Flash” on page 213 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”.
25.7.12 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 213 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low byte (0x00 - 0x02). 3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA. 4. Set OE to “1”. 25.7.
Figure 25-6. Parallel Programming Timing, Reading Sequence (within the same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE DATA tOHDZ ADDR0 (Low Byte) ADDR1 (Low Byte) DATA (High Byte) DATA (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 25-4 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 25-13.
Notes: 25.8 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock Bits commands. 2. tWLRH_CE is valid for the Chip Erase command. Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed.
To program and verify the ATmega8A in the Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Table 25-16): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during Power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2.
programmed without chip-erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least tWD_EEPROM before programming the next byte. See Table 25-15 for tWD_EEPROM value. Table 25-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FUSE 4.5 ms tWD_FLASH 4.5 ms tWD_EEPROM 9.0 ms tWD_ERASE 9.0 ms Figure 25-8.
Table 25-16. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Program Memory 0010 H000 0000 aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b.
25.9.4 SPI Serial Programming Characteristics For characteristics of the SPI module, see “SPI Timing Characteristics” on page 230.
26. Electrical Characteristics – TA = -40°C to 85°C Note: Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 26.1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C Storage Temperature .....................................
TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter RRST Reset Pull-up Resistor Rpu I/O Pin Pull-up Resistor Power Supply Current ICC Power-down mode(5) Condition Typ Max Units 30 80 k 20 50 k Active 4MHz, VCC = 3V 2 5 mA Active 8MHz, VCC = 5V 6 15 mA Idle 4MHz, VCC = 3V 0.5 2 mA Idle 8MHz, VCC = 5V 2.
26.3 Speed Grades Figure 26-1. Maximum Frequency vs. Vcc 16 MHz 8 MHz Safe Operating Area 2.7V 26.4 26.4.1 4.5V 5.5V Clock Characteristics External Clock Drive Waveforms Figure 26-2. External Clock Drive Waveforms V IH1 V IL1 26.4.2 External Clock Drive Table 26-1. External Clock Drive VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Min Max Min Max Units 0 8 0 16 MHz Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period 125 62.
Table 26-2. Notes: External RC Oscillator, Typical Frequencies R [k](1) C [pF] f(2) 33 22 650kHz 10 22 2.0MHz 1. R should be in the range 3 k - 100 k, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type. 2. The frequency will vary with package type and board layout. 26.5 System and Reset Characteristics Table 26-3.
26.6 Two-wire Serial Interface Characteristics Table 26-4 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8A Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 26-3. Table 26-4. Two-wire Serial Bus Requirements Symbol Parameter VIL VIH Vhys (1) Min Max Units Input Low-voltage -0.5 0.3 VCC V Input High-voltage 0.7 VCC VCC + 0.5 V – V 0.4 V 20 + 0.
3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency 5. This requirement applies to all ATmega8A Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. 6. The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz. 7.
Figure 26-4. SPI interface timing requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 8 7 MOSI (Data Output) MSB ... LSB Figure 26-5. SPI interface timing requirements (Slave Mode) 18 SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
26.8 ADC Characteristics Table 26-6. Symbol ADC Characteristics Max(1) Resolution Single Ended Conversion 10 Bits Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 1.75 LSB Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1MHz 3 LSB Integral Non-linearity (INL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 0.75 LSB Differential Non-linearity (DNL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 0.
27. Electrical Characteristics – TA = -40°C to 105°C Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP, TQFP, and QFN/MLF Package: 1] The sum of all IOL, for all ports, should not exceed 300 mA. 2] The sum of all IOL, for ports C0 - C5 should not exceed 100 mA.
28. Typical Characteristics – TA = -40°C to 85°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with Rail-to-Rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
Figure 28-2. Active Supply Current vs. Frequency (1 - 16MHz) 14 5.5 V 12 5.0 V ICC (mA) 10 4.5 V 8 4.0 V 6 3.6 V 3.3 V 4 2.7 V 2 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 28-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 10 -40 °C 25 °C 85 °C 9 ICC (mA) 8 7 6 5 4 3 2.5 3 3.5 4 4.5 5 5.
Figure 28-4. Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz) 6 -40 °C 5.5 25 °C 5 85 °C ICC (mA) 4.5 4 3.5 3 2.5 2 1.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-5. Active Supply Current vs. VCC (Internal RC Oscillator, 2MHz) 3.6 -40 °C 25 °C 3.2 85 °C ICC (mA) 2.8 2.4 2 1.6 1.2 2.5 3 3.5 4 4.5 5 5.
Figure 28-6. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.9 25 °C 85 °C -40 °C 1.8 1.7 ICC (mA) 1.6 1.5 1.4 1.3 1.2 1.1 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-7. Active Supply Current vs. VCC (32kHz External Oscillator) 70 25 °C 65 ICC (µA) 60 55 50 45 40 2.5 3 3.5 4 4.5 5 5.
Idle Supply Current Figure 28-8. Idle Supply Current vs. Frequency (0.1 - 1.0MHz) 0.35 5.5 V 0.3 5.0 V ICC (mA) 0.25 4.5 V 0.2 4.0 V 0.15 3.6 V 3.3 V 2.7 V 0.1 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-9. Idle Supply Current vs. Frequency (1 - 16MHz) 6 5.5 V 5 5.0 V 4 ICC (mA) 28.2 4.5 V 3 4.0 V 3.6 V 2 3.3 V 1 2.
Figure 28-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 4 -40 °C 25 °C 85 °C 3.5 ICC (mA) 3 2.5 2 1.5 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-11. Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz) -40 °C 25 °C 85 °C 2 1.8 ICC (mA) 1.6 1.4 1.2 1 0.8 0.6 2.5 3 3.5 4 4.5 5 5.
Figure 28-12. Idle Supply Current vs. VCC (Internal RC Oscillator, 2MHz) 1 85 °C 25 °C -40 °C ICC (mA) 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-13. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.5 85 °C 25 °C -40 °C ICC (mA) 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.
Figure 28-14. Idle Supply Current vs. VCC (32kHz External Oscillator) 25 ICC (uA) 20 25 °C 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 28-15. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 2.5 85 °C 2 ICC (uA) 28.3 -40 °C 25 °C 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 28-16. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 25 85 °C 25 °C -40 °C ICC (uA) 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply Current Figure 28-17. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 10 25 °C 8 ICC (uA) 28.4 6 4 2 2.5 3 3.5 4 4.5 5 5.
Standby Supply Current Figure 28-18. Standby Supply Current vs. VCC (455kHz Resonator, Watchdog Timer Disabled) 60 25 °C 50 ICC (uA) 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-19. Standby Supply Current vs. VCC (1MHz Resonator, Watchdog Timer Disabled) 60 25 °C 50 40 ICC (uA) 28.5 30 20 10 0 2.5 3 3.5 4 4.5 5 5.
Figure 28-20. Standby Supply Current vs. VCC (1MHz Xtal, Watchdog Timer Disabled) 60 25 °C 50 ICC (uA) 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-21. Standby Supply Current vs. VCC (4MHz Resonator, Watchdog Timer Disabled) 90 25 °C 75 ICC (uA) 60 45 30 15 0 2.5 3 3.5 4 4.5 5 5.
Figure 28-22. Standby Supply Current vs. VCC (4MHz Xtal, Watchdog Timer Disabled) 80 25 °C 70 60 ICC (uA) 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-23. Standby Supply Current vs. VCC (6MHz Resonator, Watchdog Timer Disabled) 100 25 °C ICC (uA) 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
Figure 28-24. Standby Supply Current vs. VCC (6MHz Xtal, Watchdog Timer Disabled) 120 25 °C 100 ICC (uA) 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-up Figure 28-25. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 100 IOP (uA) 28.
Figure 28-26. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 10 -40 °C 85 °C 25 °C 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 28-27. Reset Pull-up Resistor Current vs.
Figure 28-28. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (uA) 40 30 20 10 85 °C -40 °C 25 °C 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Pin Driver Strength Figure 28-29. I/O Pin Output Voltage vs. Source Current (VCC = 5.0V) 5 4.9 4.8 VOH (V) 28.7 4.7 4.6 -40 °C 4.5 25 °C 85 °C 4.4 4.
Figure 28-30. I/O Pin Output Voltage vs. Source Current (VCC = 3.0V) 3.5 VOH (V) 3 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0 4 8 12 16 20 IOH (mA) Figure 28-31. I/O Pin Output Voltage vs. Sink Current (VCC = 5.0V) 0.6 85 °C 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.
Figure 28-32. I/O Pin Output Voltage vs. Sink Current (VCC = 3.0V) 1 85 °C 0.8 25 °C VOL (V) 0.6 -40 °C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 28-33. Reset Pin as I/O - Pin Source Current vs. Output Voltage (VCC = 5.0V) 5 85 °C 4 Current (mA) 25 °C 3 -40 °C 2 1 0 2 2.5 3 3.5 4 4.
Figure 28-34. Reset Pin as I/O - Pin Source Current vs. Output Voltage (VCC = 2.7V) 4 -40 °C 3.5 Current (mA) 3 25 °C 2.5 2 85 °C 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 VOH (V) Figure 28-35. Reset Pin as I/O - Pin Sink Current vs. Output Voltage (VCC = 5.0V) 14 -40 °C 12 25 °C Current (mA) 10 85 °C 8 6 4 2 0 0 0.5 1 1.
Figure 28-36. Reset Pin as I/O - Pin Sink Current vs. Output Voltage (VCC = 2.7V) 4.5 -40 °C 4 3.5 25 °C Current (mA) 3 85 °C 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 VOL (V) Pin Thresholds and Hysteresis Figure 28-37. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3 85 °C 25 °C -40 °C 2.5 Threshold (V) 28.8 2 1.5 1 2.5 3 3.5 4 4.5 5 5.
Figure 28-38. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 85 °C 25 °C -40 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-39. I/O Pin Input Hysteresis vs. VCC 0.5 -40 °C 25 °C 85 °C Input Hysteresis (mV) 0.45 0.4 0.35 0.3 0.25 0.2 2.5 3 3.5 4 4.5 5 5.
Figure 28-40. Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”) 3 85 °C -40 °C 25 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-41. Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”) 2.5 25 °C 85 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 28-42. Reset Pin as I/O - Pin Hysteresis vs. VCC 0.5 85 °C -40 °C 25 °C Input Hysteresis (mV) 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-43. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”) 2.5 85 °C -40 °C 25 °C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 28-44. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”) 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-45. Reset Input Pin Hysteresis vs. VCC 0.5 Input Hysteresis (mV) 0.4 0.3 0.2 0.1 85 °C 25 °C -40 °C 0 2.5 3 3.5 4 4.5 5 5.
Bod Thresholds and Analog Comparator Offset Figure 28-46. BOD Thresholds vs. Temperature (BOD Level is 4.0V) 3.95 Rising Vcc Threshold (V) 3.9 3.85 3.8 Falling Vcc 3.75 3.7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 70 80 90 Temperature (°C) Figure 28-47. BOD Thresholds vs. Temperature (BOD Level is 2.7v) 2.8 2.75 Rising Vcc 2.7 Threshold (V) 28.9 2.65 Falling Vcc 2.6 2.55 2.
Figure 28-48. Bandgap Voltage vs. VCC 1.215 85 °C 25 °C Bandgap Voltage (V) 1.21 1.205 -40 °C 1.2 1.195 1.19 1.185 1.18 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 28-49. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) 0.003 0.002 Comparator Offset Voltage (V) 0.001 85 °C 0 25 °C -0.001 -0.002 -0.003 -40 °C -0.004 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 28-50. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.8V) 0.003 Comparator Offset Voltage (V) 0.002 25 °C 85 °C 0.001 0 -0.001 -40 °C -0.002 -0.003 -0.004 0.25 0.50 0.75 1.00 1.25 1.5 1.75 2.00 2.25 2.50 2.75 Common Mode Voltage (V) 28.10 Internal Oscillator Speed Figure 28-51. Watchdog Oscillator Frequency vs. VCC 1050 25 °C 85 °C -40 °C FRC (kHz) 1025 1000 975 950 925 2.5 3 3.5 4 4.5 5 5.
Figure 28-52. Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8,5 8 FRC (MHz) 5.5 V 7,5 4.0 V 7 2.7 V 6,5 6 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 28-53. Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.5 -40 °C 25 °C 8 FRC (MHz) 85 °C 7.5 7 6.5 6 2.5 3 3.5 4 4.5 5 5.
Figure 28-54. Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value 14 25 °C 12 FRC (MHz) 10 8 6 4 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE Figure 28-55. Calibrated 4MHz RC Oscillator Frequency vs. Temperature 4.1 4 5.5 V FRC (MHz) 3.9 4.0 V 3.8 3.7 2.7 V 3.6 3.
Figure 28-56. Calibrated 4MHz RC Oscillator Frequency vs. VCC 4.1 -40 °C 25 °C 4 85 °C FRC (MHz) 3.9 3.8 3.7 3.6 3.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-57. Calibrated 4MHz RC Oscillator Frequency vs.
Figure 28-58. Calibrated 2MHz RC Oscillator Frequency vs. Temperature 2.1 2.05 5.5 V FRC (MHz) 2 1.95 4.0 V 1.9 2.7 V 1.85 1.8 1.75 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 28-59. Calibrated 2MHz RC Oscillator Frequency vs. VCC 2.1 -40 °C 25 °C 2.05 85 °C FRC (MHz) 2 1.95 1.9 1.85 1.8 2.5 3 3.5 4 4.5 5 5.
Figure 28-60. Calibrated 2MHz RC Oscillator Frequency vs. Osccal Value 3 25 °C FRC (MHz) 2.5 2 1.5 1 0.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE Figure 28-61. Calibrated 1MHz RC Oscillator Frequency vs. Temperature 1.04 1.02 5.5 V FRC (MHz) 1 0.98 4.0 V 0.96 0.94 2.7 V 0.92 0.
Figure 28-62. Calibrated 1MHz RC Oscillator Frequency vs. VCC 1.04 -40 °C 25 °C 1.02 85 °C FRC (MHz) 1 0.98 0.96 0.94 0.92 0,9 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-63. Calibrated 1MHz RC Oscillator Frequency vs. Osccal Value 1.6 25 °C 1.4 FRC (MHz) 1.2 1 0.8 0.6 0.4 0.
28.11 Current Consumption of Peripheral Units Figure 28-64. Brown-out Detector Current vs. VCC 20 -40 °C 25 °C 16 ICC (uA) 85 °C 12 8 4 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-65. ADC Current vs. VCC (AREF = AVCC) 300 275 -40 °C 25 °C 85 °C 250 ICC (uA) 225 200 175 150 125 100 2.5 3 3.5 4 4.5 5 5.
Figure 28-66. AREF External Reference Current vs. VCC 85 °C 25 °C -40 °C 160 140 ICC (uA) 120 100 80 60 40 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-67. 32kHz TOSC Current vs. VCC (Watchdog Timer Disabled) 10 85 °C 25 °C ICC (uA) 8 -40 °C 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
Figure 28-68. Watchdog Timer Current vs. VCC 20 85 °C 25 °C -40 °C ICC (uA) 16 12 8 4 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-69. Analog Comparator Current vs. VCC 70 85 °C 60 25 °C ICC (uA) 50 -40 °C 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.
Figure 28-70. Programming Current vs. VCC 6 -40 °C 5 25 °C ICC (mA) 4 85 °C 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.12 Current Consumption in Reset and Reset Pulsewidth Figure 28-71. Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) 3 5.5 V 5.0 V 2.5 ICC (mA) 4.5 V 2 4.0 V 3.6 V 3.3 V 1.5 2.7 V 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 28-72. Reset Supply Current vs. VCC (1 - 16MHz, Excluding Current Through The Reset Pull-up) 12 5.5 V 10 5.0 V 4.5 V ICC (mA) 8 6 4.0 V 3.6 V 4 3.3 V 2.7 V 2 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 28-73. Reset Pulse Width vs.
29. Typical Characteristics – TA = -40°C to 105°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off.
Figure 29-2. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) 5.5 -40 °C 5 25 °C 85 °C 105 °C 4.5 ICC (mA) 4 3.5 3 2.5 2 1.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-3. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) 3.5 -40 °C 3.25 25 °C 3 85 °C 105 °C ICC (mA) 2.75 2.5 2.25 2 1.75 1.5 1.25 1 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 29-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 1.8 25 °C -40 °C 85 °C 105 °C 1.7 1.6 ICC (mA) 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-5. Active Supply Current vs. VCC (32 kHz External Oscillator) 105 °C 85 °C 25 °C -40 °C 65 62 59 ICC (uA) 56 53 50 47 44 41 38 35 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Idle Supply Current Figure 29-6. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 4.2 -40 °C 25 °C 85 °C 105 °C 3.9 3.6 ICC (mA) 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-7. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) 2.1 -40 °C 25 °C 85 °C 105 °C 1.9 1.7 ICC (mA) 29.1.2 1.5 1.3 1.1 0.9 0.7 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 29-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) 105 °C 85 °C 25 °C -40 °C 0.9 0.8 ICC (mA) 0.7 0.6 0.5 0.4 0.3 0.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 0.5 105 °C 85 °C 25 °C -40 °C 0.45 0.4 ICC (mA) 0.35 0.3 0.25 0.2 0.15 0.1 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 29-10. Idle Supply Current vs. VCC (32 kHz External RC Oscillator) 24.5 105 °C 22.5 85 °C 20.5 25 °C -40 °C ICC (uA) 18.5 16.5 14.5 12.5 10.5 8.5 6.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Power-down Supply Current Figure 29-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 4.5 105 °C 4 3.5 3 ICC (uA) 29.1.3 2.5 85 °C 2 1.5 -40 °C 25 °C 1 0.5 0 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 29-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 24 105 °C 85 °C 25 °C -40 °C 21 ICC (uA) 18 15 12 9 6 3 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Power-save Supply Current Figure 29-13. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 15 105 °C 14 13 85 °C 12 11 ICC (uA) 29.1.4 25 °C -40 °C 10 9 8 7 6 5 4 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
29.1.5 Standby Supply Current Figure 29-14. Standby Supply Current vs. VCC (32 kHz External RC Oscillator) 25 105 °C 23 85 °C 21 25 °C -40 °C ICC (uA) 19 17 15 13 11 9 7 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Pin Pull-up Figure 29-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 100 IOP (uA) 29.1.6 80 60 40 85 °C 25 °C -40 °C 105 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 29-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 85 °C 25 °C -40 °C 105 °C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VOP (V) Figure 29-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 110 100 90 80 IRESET (uA) 70 60 50 40 30 25 °C -40 °C 85 °C 105 °C 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 29-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 105 °C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET (V) Pin Driver Strength Figure 29-19. I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5.1 5 4.9 4.8 VOH (V) 29.1.7 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 105 °C 4.
Figure 29-20. I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.1 2.9 VOH (V) 2.7 2.5 -40 °C 2.3 25 °C 2.1 85 °C 105 °C 1.9 1.7 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 29-21. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 105 °C 85 °C 0.6 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.
Figure 29-22. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 1 105 °C 85 °C 0.9 0.8 0.7 25 °C VOL (V) 0.6 -40 °C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL(mA) Pin Threshold and Hysteresis Figure 29-23. I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) 3 105 °C 85 °C 25 °C -40 °C 2.8 2.6 Threshold (V) 29.1.8 2.4 2.2 2 1.8 1.6 1.4 1.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 29-24. I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 2.5 105 °C 85 °C 25 °C -40 °C Threshold (V) 2.2 1.9 1.6 1.3 1 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-25. I/O Pin Input Hysteresis vs. VCC 0.5 85 °C 105 °C Input Hysteresis (mV) 0.45 0.4 0.35 -40 °C 25 °C 0.3 0.25 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 29-26. Reset Pin as I/O - Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) 3.1 -40 °C 25 °C 85 °C 105 °C Threshold (V) 2.8 2.5 2.2 1.9 1.6 1.3 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-27. Reset Pin as I/O - Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 105 °C 85 °C 25 °C -40 °C 2.3 2.1 Threshold (V) 1.9 1.7 1.5 1.3 1.1 0.9 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 29-28. Reset Pin as I/O - Pin Hysteresis vs. VCC -40 °C 25 °C 85 °C 105 °C 0.7 Input Hysteresis (mV) 0.65 0.6 0.55 0.5 0.45 0.4 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-29. Reset Input Threshold vs. VCC (VIH , Reset Pin Read as ‘1’) -40 °C 25 °C 85 °C 105 °C 2.5 2.3 Threshold (V) 2.1 1.9 1.7 1.5 1.3 1.1 0.9 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 29-30. Reset Input Threshold vs. VCC (VIL, Reset Pin Read as ‘0’) 2.4 105 °C 85 °C 25 °C -40 °C 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-31. Reset Pin Input Hysteresis vs. VCC 0.5 0.45 Input Hysteresis (mV) 0.4 0.35 0.3 -40 °C 0.25 25 °C 0.2 0.15 105 °C 85 °C 0.1 0.05 0 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
BOD Threshold Figure 29-32. BOD Threshold vs. Temperature (VCC = 4.3V) 4 Rising Vcc 3.98 3.96 Threshold (V) 3.94 3.92 3.9 3.88 Falling Vcc 3.86 3.84 3.82 3.8 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Figure 29-33. BOD Threshold vs. Temperature (VCC = 2.7V) 2.63 Rising Vcc 2.61 2.59 Threshold (V) 29.1.9 2.57 2.55 2.53 Falling Vcc 2.51 2.49 2.
Figure 29-34. Bandgap Voltage vs. Temperature 1.215 1.21 5.5V Bandgap Voltage (V) 1.205 5.0V 1.2 4.0V 3.3V 2.7V 1.195 1.19 1.185 1.8V 1.18 1.175 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Figure 29-35. Bandgap Voltage vs. VCC 1.215 25 °C 85 °C 105 °C -40 °C 1.21 Bandgap Voltage (V) 1.205 1.2 1.195 1.19 1.185 1.18 1.175 1.5 2 2.5 3 3.5 4 4.5 5 5.
Internal Oscillator Speed Figure 29-36. Watchdog Oscillator Frequency vs. VCC 25 °C -40 °C 85 °C 105 °C 1120 1100 FRC (kHz) 1080 1060 1040 1020 1000 980 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-37. Watchdog Oscillator Frequency vs. Temperature 1130 1110 5.5 V 1090 1070 FRC (kHz) 29.1.10 5.0 V 1050 4.5 V 4.0 V 3.6 V 1030 1010 2.
Figure 29-38. Calibrated 8 MHz RC Oscillator vs. Temperature 8.4 8.2 8 FRC (MHz) 7.8 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 7.6 7.4 7.2 7 3.0 V 6.8 2.7 V 6.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Figure 29-39. Calibrated 8 MHz RC Oscillator vs. VCC 8.4 -40 °C 8.2 25 °C 8 85 °C 105 °C FRC (MHz) 7.8 7.6 7.4 7.2 7 6.8 6.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 29-40. Calibrated 8 MHz RC Oscillator vs. OSCCAL Value 14 -40 °C 25 °C 85 °C 105 °C 12 FRC (MHz) 10 8 6 4 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Figure 29-41. Calibrated 4 MHz RC Oscillator vs. Temperature 4.15 4.05 FRC (MHz) 3.95 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.85 3.75 3.0 V 3.65 2.7 V 3.
Figure 29-42. Calibrated 4 MHz RC Oscillator vs. VCC 4.1 -40 °C 4.05 25 °C 4 85 °C 105 °C FRC (MHz) 3.95 3.9 3.85 3.8 3.75 3.7 3.65 3.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-43. Calibrated 4 MHz RC Oscillator vs.
Figure 29-44. Calibrated 2 MHz RC Oscillator vs. Temperature 2.05 2.02 1.99 5.5 V FRC (MHz) 1.96 5.0 V 4.5 V 4.0 V 3.6 V 1.93 1.9 1.87 1.84 3.0 V 2.7 V 1.81 1.78 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Figure 29-45. Calibrated 2 MHz RC Oscillator vs. VCC 2.07 -40 °C 25 °C 2.04 2.01 85 °C 105 °C FRC (MHz) 1.98 1.95 1.92 1.89 1.86 1.83 1.8 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 29-46. Calibrated 2 MHz RC Oscillator vs. OSCCAL Value 3.5 -40 °C 25 °C 85 °C 105 °C 3.2 2.9 FRC (MHz) 2.6 2.3 2 1.7 1.4 1.1 0.8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Figure 29-47. Calibrated 1 MHz RC Oscillator vs. Temperature 1.03 1.01 5.5 V FRC (MHz) 0.99 5.0 V 4.5 V 4.0 V 3.6 V 0.97 0.95 3.0 V 2.7 V 0.93 0.
Figure 29-48. Calibrated 1 MHz RC Oscillator vs. VCC FRC (MHz) 1.04 1.02 -40 °C 25 °C 1 85 °C 105 °C 0.98 0.96 0.94 0.92 0.9 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-49. Calibrated 1 MHz RC Oscillator vs. OSCCAL Value 1.8 -40 °C 25 °C 85 °C 105 °C 1.6 FRC (MHz) 1.4 1.2 1 0.8 0.6 0.4 0.
Current Consumption of Peripheral Units Figure 29-50. Brown-out Detector Current vs. VCC 18 -40 °C 17 25 °C 16 ICC (uA) 15 85 °C 105 °C 14 13 12 11 10 9 8 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-51. ADC Current vs. VCC (AREF = AVCC) 300 -40 °C 25 °C 85 °C 105 °C 280 260 240 ICC (uA) 29.1.11 220 200 180 160 140 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 29-52. Watchdog Timer Current vs. VCC 20 85 °C 105 °C 25 °C -40 °C 18 16 ICC (uA) 14 12 10 8 6 4 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 29-53. Analog Comparator Current vs. VCC 72 105 °C 68 85 °C 64 ICC (mA) 60 25 °C 56 52 48 -40 °C 44 40 36 32 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 29-54. Programming Current vs. VCC 6 -40 °C 5 25 °C ICC (mA) 4 85 °C 105 °C 3 2 1 0 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Current Consumption in Reset and Reset Pulsewidth Figure 29-55. Reset Supply Current vs. Vcc (0.1 - 1.0 MHz, Excluding Current Through the Reset Pull-up) 3 5.5 V ICC (mA) 29.1.12 2.5 5.0 V 2 4.5 V 4.0 V 3.6 V 1.5 2.7 V 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 29-56. Reset Supply Current vs. Vcc (1 - 16 MHz, Excluding Current Through the Reset Pull-up) 12 5.5 V 10 5.0 V ICC (mA) 8 4.5 V 4.0 V 6 3.6 V 4 2.7 V 2 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 29-57. Minimum Reset Pulsewidth vs. Vcc 800 700 Pulsewidth (ns) 600 500 400 105 °C 85 °C 25 °C -40 °C 300 200 100 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
30.
Note: 1. Refer to the USART description for details on how to access UBRRH and UCSRC. 2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag.
31.
31. Instruction Set Summary (Continued) DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word Rd Rr Rd+1:Rd Rr+1:Rr LDI Rd, K Load Immediate Rd K None 1 LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2 2 None 1 None 1 LD Rd, Y Load Indirect Rd (Y) None LD Rd, Y+ Load Indirect and Post-Inc.
31. Instruction Set Summary (Continued) NOP SLEEP WDR No Operation Sleep Watchdog Reset (see specific descr. for Sleep function) (see specific descr.
32. Ordering Information Speed (MHz) Power Supply (V) 16 Notes: 2.7 - 5.5 Ordering Code(2) Package(1) ATmega8A-AU ATmega8A-AUR(3) ATmega8A-PU ATmega8A-MU ATmega8A-MUR(3) 32A 32A 28P3 32M1-A 32M1-A Industrial (-40C to 85C) ATmega8A-AN ATmega8A-ANR(3) ATmega8A-PN ATmega8A-MN ATmega8A-MNR(3) 32A 32A 28P3 32M1-A 32M1-A Extended (-40C to 105C)(4) Operation Range 1. This device can also be supplied in wafer form.
33. Packaging Information 33.1 32A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
33.2 28P3 D PIN 1 E1 A SEATING PLANE L B2 B1 A1 B (4 PLACES) 0º ~ 15º REF e E C COMMON DIMENSIONS (Unit of Measure = mm) eB Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). MIN NOM MAX – – 4.5724 A1 0.508 – – D 34.544 – 34.798 E 7.620 – 8.255 E1 7.112 – 7.493 B 0.381 – 0.533 B1 1.143 – 1.397 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.
32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A K 0.08 C P D2 1 2 3 P Pin #1 Notch (0.20 R) K e SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 E2 b COMMON DIMENSIONS (Unit of Measure = mm) L BOTTOM VIEW 0.20 REF b 0.18 0.23 0.30 D 4.90 5.00 5.10 D1 4.70 4.75 4.80 D2 2.95 3.10 3.25 5.10 E 4.90 5.00 E1 4.70 4.75 4.80 E2 2.95 3.10 3.25 e Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
The revision letter in this section refers to the revision of the ATmega8A device. 34.1 ATmega8A, rev.
5. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR.
35. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section refers to the document revision. 35.1 35.2 35.3 Rev.8159E – 02/2013 1. Applied the Atmel new page layout for datasheets including new logo and last page. 2. Removed the reference to the debuggers and In-Circuit Emulators. 3. Added “Capacitive touch sensing” on page 6. 4.
35.5 Rev.8159A – 08/08 1. Initial revision (Based on the ATmega8/L datasheet 2486T-AVR-05/08) 2. Changes done compared to ATmega8/L datasheet 2486T-AVR-05/08: – All Electrical Characteristics are moved to “Electrical Characteristics – TA = -40°C to 85°C” on page 225. – Updated “DC Characteristics” on page 225 with new VOL Max (0.9V and 0.6V) and typical value for ICC. – Added “Speed Grades” on page 227. – Added a new sub section “System and Reset Characteristics” on page 228.
Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 3 2.1 Block Diagram ...................................................................................................3 2.2 Pin Descriptions ...............
9.8 Timer/Counter Oscillator ..................................................................................30 9.9 Register Description ........................................................................................31 10 Power Management and Sleep Modes ................................................. 32 10.1 Sleep Modes ....................................................................................................32 10.2 Idle Mode ...................................................
15.7 Register Description ........................................................................................69 16 Timer/Counter0 and Timer/Counter1 Prescalers ................................. 71 16.1 Overview ..........................................................................................................71 16.2 Internal Clock Source ......................................................................................71 16.3 Prescaler Reset ...........................................
19.4 Data Modes ...................................................................................................121 19.5 Register Description ......................................................................................123 20 USART ................................................................................................... 125 20.1 Features ........................................................................................................125 20.2 Overview .....................
23.8 Register Description ......................................................................................190 24 Boot Loader Support – Read-While-Write Self-Programming ......... 194 24.1 Features ........................................................................................................194 24.2 Overview ........................................................................................................194 24.3 Application and Boot Loader Flash Sections ........................
28.3 Power-down Supply Current ..........................................................................242 28.4 Power-save Supply Current ...........................................................................243 28.5 Standby Supply Current ................................................................................244 28.6 Pin Pull-up .....................................................................................................247 28.7 Pin Driver Strength .........................
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