Datasheet

96
ATmega8A [DATASHEET]
8159E–AVR–02/2013
17.11.3 TCNT1H and TCNT1L – Timer/Counter 1
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read
and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and Low bytes are
read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See
“Accessing 16-bit Registers” on page 75.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a Compare Match between
TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the Compare Match on the following timer clock for all compare
units.
17.11.4 OCR1AH and OCR1AL– Output Compare Register 1 A
17.11.5 OCR1BH and OCR1BL – Output Compare Register 1 B
The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value
(TCNT1). A match can be used to generate an Output Compare Interrupt, or to generate a waveform output on the
OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes are written simulta-
neously when the CPU writes to these registers, the access is performed using an 8-bit temporary High byte
Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Regis-
ters” on page 75.
17.11.6 ICR1H and ICR1L – Input Capture Register 1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or
optionally on the Analog Comparator Output for Timer/Counter1). The Input Capture can be used for defining the
counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit temporary High byte Register
Bit 76543210
TCNT1[15:8] TCNT1H
TCNT1[7:0] TCNT1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR1A[15:8] OCR1AH
OCR1A[7:0] OCR1AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR1B[15:8] OCR1BH
OCR1B[7:0] OCR1BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
ICR1[15:8] ICR1H
ICR1[7:0] ICR1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000