Datasheet

68
ATmega8A [DATASHEET]
8159E–AVR–02/2013
15.6 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore shown as a clock enable signal
in the following figures. The figures include information on when Interrupt Flags are set. Figure 15-3 contains timing
data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value.
Figure 15-3. Timer/Counter Timing Diagram, No Prescaling
Figure 15-4 shows the same timing data, but with the prescaler enabled.
Figure 15-4. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)