Datasheet

ATmega8A [DATASHEET]

8159E–AVR–02/2013

13. I/O Ports

13.1 Overview

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that

the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the

SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/dis-

abling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with

both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins

have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection

diodes to both V

and Ground as indicated in Figure 13-1. Refer to “Electrical Characteristics – TA = -40°C to

85°C” on page 225 for a complete list of parameters.

Figure 13-1. I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower case “x” represents the number-

ing letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit

defines in a program, the precise form must be used (i.e., PORTB3 for bit 3 in Port B, here documented generally

as PORTxn). The physical I/O Registers and bit locations are listed in “Register Description” on page 62.

Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data

Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the

Data Register and the Data Direction Register are read/write. In addition, the Pull-up Disable – PUD bit in SFIOR

disables the pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 50. Most port pins

are multiplexed with alternate functions for the peripheral features on the device. How each alternate function inter-

feres with the port pin is described in “Alternate Port Functions” on page 54. Refer to the individual module sections

for a full description of the alternate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port

as general digital I/O.

Logic

See Figure

"General Digital I/O" for

Details

Pxn