Datasheet

40
ATmega8A [DATASHEET]
8159E–AVR–02/2013
11.4 Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at
V
CC
= 5V. See characterization data for typical values at other V
CC
levels. By controlling the Watchdog Timer pres-
caler, the Watchdog Reset interval can be adjusted as shown in Table 11-7 on page 40. The WDR – Watchdog
Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a
Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega8A resets and executes from the Reset Vector. For
timing details on the Watchdog Reset, refer to “Watchdog Reset” on page 39.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watch-
dog is disabled. Refer to the description of the Watchdog Timer Control Register for details.
Figure 11-7. Watchdog Timer
11.5 Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing the Watchdog Timer configuration differs slightly between the safety levels. Separate
procedures are described for each level.
WATCHDOG
OSCILLATOR
Assembly Code Example