Datasheet

193
ATmega8A [DATASHEET]
8159E–AVR–02/2013
23.8.3 ADCL and ADCH – The ADC Data Register
23.8.3.1 ADLAR = 0
23.8.3.2 ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read
first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If
ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.
• ADC9:0: ADC Conversion result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 190.
Bit 151413121110 9 8
– – – – – – ADC9 ADC8 ADCH
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
00000000
Bit 151413121110 9 8
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
ADC1 ADC0 – – – – – – ADCL
76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
00000000