Datasheet

185
ATmega8A [DATASHEET]
8159E–AVR–02/2013
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC
clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC
Data Registers, and ADIF is set. In single conversion mode, ADSC is cleared simultaneously. The software may
then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC
remains high. For a summary of conversion times, see Table 23-1.
Figure 23-3. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 23-4. ADC Timing Diagram, Single Conversion
Figure 23-5. ADC Timing Diagram, Free Running Conversion
MSB of Result
LSB of Result
ADC Clock
ADSC
Sample & Hold
ADIF
ADCH
ADCL
Cycle Number
ADEN
1 212
13
14 15
16 17
18
19 20 21 22 23
24 25
1 2
First Conversion
Next
Conversion
3
MUX and REFS
Update
MUX and REFS
Update
Conversion
Complete
1
2 3 4 5 6 7 8
9 10 11 12 13
MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update
11 12 13
MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
34
Conversion
Complete
Sample &Hold
MUX and REFS
Update