Datasheet

180
ATmega8A [DATASHEET]
8159E–AVR–02/2013
Note: 1. ADC7:6 are only available in TQFP and QFN/MLF Package.
22.3 Register Description
22.3.1 SFIOR – Special Function IO Register
• Bit 3 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer
selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the neg-
ative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed
Input” on page 179.
22.3.2 ACSR – Analog Comparator Control and Status Register
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any
time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When chang-
ing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an
interrupt can occur when the bit is changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When
this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference”
on page 39.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization
introduces a delay of 1 - 2 clock cycles.
1 0 001 ADC1
1 0 010 ADC2
1 0 011 ADC3
1 0 100 ADC4
1 0 101 ADC5
1 0 110 ADC6
1 0 111 ADC7
Table 22-1. Analog Comparator Multiplexed Input
(1)
ACME ADEN MUX2:0 Analog Comparator Negative Input
Bit 7 6 5 4 3 2 1 0
– – – – ACME PUD PSR2 PSR10 SFIOR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value00N/A00000