Datasheet

15
ATmega8A [DATASHEET]
8159E–AVR–02/2013
8. AVR Memories
8.1 Overview
This section describes the different memories in the Atmel
®
AVR
®
ATmega8A. The AVR architecture has two main
memory spaces, the Data memory and the Program Memory space. In addition, the ATmega8A features an
EEPROM Memory for data storage. All three memory spaces are linear and regular.
8.2 In-System Reprogrammable Flash Program Memory
The ATmega8A contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since
all AVR instructions are 16- or 32-bits wide, the Flash is organized as 4K x 16 bits. For software security, the Flash
Program memory space is divided into two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8A Program Counter (PC)
is 12 bits wide, thus addressing the 4K Program memory locations. The operation of Boot Program section and
associated Boot Lock Bits for software protection are described in detail in “Boot Loader Support – Read-While-
Write Self-Programming” on page 194. “Memory Programming” on page 207 contains a detailed description on
Flash Programming in SPI- or Parallel Programming mode.
Constant tables can be allocated within the entire Program memory address space (see the LPM – Load Program
memory instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 11.
Figure 8-1. Program Memory Map
$000
$FFF
Application Flash Section
Boot Flash Section