Datasheet

146
ATmega8A [DATASHEET]
8159E–AVR–02/2013
The UCSRC Register shares the same I/O location as the UBRRH Register. See the “Accessing UBRRH/UCSRC
Registers” on page 142 section which describes how to access this register.
• Bit 7 – URSEL: Register Select
This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when reading UCSRC.
The URSEL must be one when writing the UCSRC.
• Bit 6 – UMSEL: USART Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.
• Bit 5:4 – UPM1:0: Parity Mode
These bits enable and set type of Parity Generation and Check. If enabled, the Transmitter will automatically gen-
erate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value
for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE Flag in UCSRA will be
set.
• Bit 3 – USBS: Stop Bit Select
This bit selects the number of stop bits to be inserted by the trAnsmitter. The Receiver ignores this setting.
• Bit 2:1 – UCSZ1:0: Character Size
The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character Size) in a frame
the Receiver and Transmitter use.
Table 20-4. UMSEL Bit Settings
UMSEL Mode
0 Asynchronous Operation
1 Synchronous Operation
Table 20-5. UPM Bits Settings
UPM1 UPM0 Parity Mode
0 0 Disabled
01Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Table 20-6. USBS Bit Settings
USBS Stop Bit(s)
01-bit
12-bit
Table 20-7. UCSZ Bits Settings
UCSZ2 UCSZ1 UCSZ0 Character Size
0005-bit
0016-bit
0107-bit
0118-bit