Datasheet

127
ATmega8A [DATASHEET]
8159E–AVR–02/2013
• Transmit Buffer Functionality.
• Receiver Operation.
However, the receive buffering has two improvements that will affect the compatibility in some special cases:
• A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer.
Therefore the UDR must only be read once for each incoming data! More important is the fact that the Error
Flags (FE and DOR) and the ninth data bit (RXB8) are buffered with the data in the receive buffer. Therefore the
status bits must always be read before the UDR Register is read. Otherwise the error status will be lost since
the buffer state is lost.
• The Receiver Shift Register can now act as a third buffer level. This is done by allowing the received data to
remain in the serial Shift Register (see Figure 20-1) if the Buffer Registers are full, until a new start bit is
detected. The USART is therefore more resistant to Data OverRun (DOR) error conditions.
The following control bits have changed name, but have same functionality and register location:
• CHR9 is changed to UCSZ2.
• OR is changed to DOR.
20.3 Clock Generation
The clock generation logic generates the base clock for the Transmitter and Receiver. The USART supports four
modes of clock operation: normal asynchronous, double speed asynchronous, Master synchronous and Slave
Synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asyn-
chronous and synchronous operation. Double speed (Asynchronous mode only) is controlled by the U2X found in
the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin
(DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is
only active when using Synchronous mode.
Figure 20-2 shows a block diagram of the clock generation logic.
Figure 20-2. Clock Generation Logic, Block Diagram
Signal description:
txclk Transmitter clock. (Internal Signal)
rxclk Receiver base clock. (Internal Signal)
xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
Prescaling
Down-Counter
/ 2
UBRR
/ 4 / 2
fosc
UBRR+1
Sync
Register
OSC
XCK
Pin
txclk
U2X
UMSEL
DDR_XCK
0
1
0
1
xcki
xcko
DDR_XCK
rxclk
0
1
1
0
Edge
Detector
UCPOL