Datasheet

126
ATmega8A [DATASHEET]
8159E–AVR–02/2013
Figure 20-1. USART Block Diagram
(1)
Note: 1. Refer to “Pin Configurations” on page 2, Table 13-10 on page 62, and Table 13-9 on page 62 for USART pin
placement.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock
generator, Transmitter and Receiver. Control Registers are shared by all units. The clock generation logic consists
of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator.
The XCK (transfer clock) pin is only used by synchronous transfer mode. The Transmitter consists of a single write
buffer, a serial Shift Register, Parity Generator and control logic for handling different serial frame formats. The
write buffer allows a continuous transfer of data without any delay between frames. The Receiver is the most com-
plex part of the USART module due to its clock and data recovery units. The recovery units are used for
asynchronous data reception. In addition to the recovery units, the Receiver includes a parity checker, control
logic, a Shift Register and a two level receive buffer (UDR). The Receiver supports the same frame formats as the
Transmitter, and can detect Frame Error, Data OverRun and Parity Errors.
20.2.1 AVR USART vs. AVR UART – Compatibility
The USART is fully compatible with the AVR UART regarding:
• Bit locations inside all USART Registers.
• Baud Rate Generation.
• Transmitter Operation.
PARITY
GENERATOR
UBRR[H:L]
UDR (Transmit)
UCSRA UCSRB UCSRC
BAUD RATE GENERATOR
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER RxD
TxD
PIN
CONTROL
UDR (Receive)
PIN
CONTROL
XCK
DATA
RECOVERY
CLOCK
RECOVERY
PIN
CONTROL
TX
CONTROL
RX
CONTROL
PARITY
CHECKER
DATABUS
OSC
SYNC LOGIC
Clock Generator
Transmitter
Receiver